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* of: Drop devicetree merge supportSascha Hauer2014-05-221-1/+1
| | | | | | | | | | | | I assume I am the only person knowing that barebox is able to merge devicetrees. This feature seems broken for a while now since trying to merge devicetress results in: unflatten: too many end nodes Remove this feature to save the complexity. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* rework debug_llSascha Hauer2013-09-051-1/+1
| | | | | | | | | | Convert to static inline functions and use lower case letters for function names. Also, include mach/debug_ll.h when an architecture provides support for debug_ll, not only when it's actually enabled. This allows architecures to put some UART initialization code into mach/debug_ll.h which is compiled out when debug_ll is disabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: remove extra copyrightsAntony Pavlov2013-06-181-1/+0
| | | | | | | | | Remove Shinya Kuribayashi's copyright on the ADR macro in start-pbl.S as we don't define this macro in this file or even use it where. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add initial device tree supportAntony Pavlov2013-05-132-0/+63
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: initialize malloc pool before start_barebox()Sascha Hauer2013-03-141-0/+5
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pbl: factorise decompressorJean-Christophe PLAGNIOL-VILLARD2013-01-301-22/+2
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add pre-bootloader (pbl) image supportAntony Pavlov2012-12-143-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on ARM pbl support and allows creating a pre-bootloader binary for compressed image. For different MIPS SoCs (or even for different boards based on the same SoC) the operations carried on in start-pbl.S can be very different. The additional constraints can be imposed on the size of the boot code or the special magic labels in the beginning of the boot code; In some cases it could be necessary to show CPU is alive as early as possible (transmit a char via UART or blink a LED). So the demands for pbl start operation can be very different. E.g. malta board store boot code at the NOR flash mapped to the MIPS power-on address (0xbfc00000); it is the most simple case: we need just copy pbl image from direct-mapped flash to RAM and jump there. The XBurst-powered boards store boot code in the beginning of a NAND flash or in the beginning of SD/MMC card. In this case we must use simple and short NAND or SD/MMC access routines to copy pbl image to RAM. To meet so different demands a simple technique is selected: * MIPS pbl entry point located in file arch/mips/boot/start-pbl.S. * MIPS pbl code (see start-pbl.S) assumes that every pbl-enabled board has a arch/mips/boards/<BOARD>/include/board/board_pbl_start.h header file. This file must contain definition of the board_pbl_start macro. This macro is used as start of pbl image; * the most popular asm routines (stack setup, relocation to link address, NS16550 initialization (WIP) and so on) are containt in the arch/mips/include/asm/pbl_macros.h header file. So board pbl macro can use it if necessary. It is possible to create similar headers with macros for each specific SoC; so even if we have many different boards based on the same SoC the board_pbl_start macro for every board can be short and clear. * after board-specific initialization the stack pointer is initialized and pbl C code is started. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: main_entry.c: fix typoAntony Pavlov2012-11-191-1/+0
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Treewide: remove address of the Free Software FoundationSascha Hauer2012-09-172-7/+0
| | | | | | | The FSF address has changed in the past. Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add initial exceptions handlingAntony Pavlov2012-07-271-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | Checking exception handling: $ make qemu-malta_defconfig $ make ... $ qemu-system-mips -nodefaults -M malta -m 256 \ -nographic -serial stdio -bios ./barebox.bin ... barebox:/ md -l 0x03 Ooops, address error on load or ifetch! EPC = 0xa082783c CP0_STATUS = 0x00000006 CP0_CAUSE = 0x00000410 CP0_CONFIG = 0x80008482 ### ERROR ### Please RESET the board ### Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: import CPU and cache detection code from Linux 3.4Antony Pavlov2012-05-231-0/+9
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: introduce C architecture-specific low-level initAntony Pavlov2012-05-233-12/+46
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: start.S: add "barebox" label at _start + 0x10Antony Pavlov2012-05-111-0/+12
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: start.S: clean up whitespacesAntony Pavlov2012-04-261-1/+1
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add common MIPS stuffAntony Pavlov2011-08-052-0/+144
Add start.S, CP0 clocksource, Makefile, linker script and memory layout function. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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