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* MIPS: dts: use physical addresses (as Linux does)Antony Pavlov2014-09-111-7/+7
| | | | | | | | With IOMEM() adapted for MIPS we can use physical addresses in device tree reg property. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: dts: qemu-malta.dts: use i2c-gpio for accessing CBUS FPGA I2C busAntony Pavlov2014-06-251-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also we can enable m24c02 eeprom chip in dts-file e.g. &i2c0 { status = "okay"; eeprom: m24c02@50 { compatible = "spd"; reg = <0x50>; }; }; Alas! qemu mips malta spd m24c02 eeprom chip emulation is not perfect: the block read operation does not work properly. Here is an example. If we read eeprom content byte-by-byte then there is no problem: barebox:/ for i in 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f ; > do i2c_read -b 0 -a 0x50 -r $i -c 1 ; done 0x01 0x75 0x54 0x00 0x82 0x08 0x00 0x01 Compare this output with content of qemu.git/hw/mips/mips_malta.c: static eeprom24c0x_t spd_eeprom = { .contents = { ... /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01, But if we read several bytes at once the we have data corruption: barebox:/ i2c_read -b 0 -a 0x50 -r 0x8 -c 8 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: dts: qemu-malta.dts: enable CBUS FPGA I2C gpio driverAntony Pavlov2014-06-241-0/+7
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: qemu-malta: add CBUS UART supportAntony Pavlov2014-04-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds CBUS UART dts support; also it adds the necessary macros for DEBUG_LL. qemu-malta supports three serial interfaces: * two ports are provided by the FDC37M817 Super I/O; this chip is connected via LPC bus to Intel 82371EB (PIIX4E) South Bridge; * the third serial port is provided by the discrete TI 16C550C (CBUS UART); this chip is connected via CBUS directly to the board's GT64120 North Bridge. See Malta User's Manual (MD00048) for details. CBUS UART Instructions for use: 1. Enable CONFIG_CONSOLE_ACTIVATE_ALL in .config (or disable uart0 in dts) and compile barebox; 2. run qemu: qemu-system-mips -nographic -nodefaults \ -monitor null -M malta -m 256 \ -serial null -serial null -serial stdio \ -bios barebox-flash-image Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: qemu-malta: use YAMON-style GT64120 memory mapAntony Pavlov2013-10-281-2/+2
| | | | | | | | | | | | | There are some reasons for using YAMON-style memory map: * we can run Linux kernel from barebox; * we can use GXemul for running barebox. YAMON-style GT64120 memory map make move UART to the new position. The files gt64120.h and mach-gt64120.h are imported from Linux. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: qemu-malta: switch to devicetreeAntony Pavlov2013-09-041-0/+33
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: qemu-malta: add device tree supportAntony Pavlov2013-05-131-0/+12
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>