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* MIPS: drop redundant debug_ll_outhexw macro definesAntony Pavlov2017-01-102-32/+31
| | | | | | | | | | | | The debug_ll_outhexw macro has no dependency on UART model so we can remove it from UART-dependent header files (debug_ll_ns16550.h and mach-ath79/.../debug_ll.h). On the other hand the only debug_ll_outhexw user is MIPS nmon monitor so we can move the debug_ll_outhexw macro to pbl_nmon.h. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: implement dma_sync_* functionsPeter Mamonov2016-03-091-1/+10
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: flush cache on shutdownAntony Pavlov2016-03-091-0/+6
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add initial R4000-style cache supportAntony Pavlov2016-03-092-0/+10
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: import cache init code from U-Boot v2016.01-212-ga3ab2aeAntony Pavlov2016-03-093-0/+170
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: import optimized string functions from LinuxAleksey Kuleshov2015-11-261-1/+8
| | | | | | | | | 10x performance gain according to simple test on QEMU malta: barebox:/ time memcpy 0xa0000000 0xa0001000 0x100000 Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru> Acked-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add pbl_blt macroOleksij Rempel2015-11-131-0/+12
| | | | | | | | | | | | | | | | | | | | | | Barebox' PBL is able to initialize SoC's memory controller, but it can be used only if PBL runs from ROM or on-chip SRAM. MIPS architecture standard boot vector is 0xbfc00000 so on most MIPS SoCs all addresses higher than 0xbfc00000 belong to boot ROM or on-chip SRAM. Thus there's a simple criterion to check if PBL runs from ROM: just check if current PC is higher than 0xbfc00000. Some MIPS boards have ROM start address lower than 0xbfc00000 so it's reasonable to make ROM start address checking board-dependant. The pbl_blt macro checks if current pc is lower than the first argument (ROM start address). If so then next instruction executed is defined by the second argument of the macro. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Tested-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: allow user to pass incorrect address to md commandAntony Pavlov2015-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | This commit makes it possible to handle exception on incorrect data access so 'md' command just show 'xxxxxxxx' instead of crashing the system. barebox:/ md -l 0xa0000003+4 a0000003: xxxxxxxx .... Without this commit we will get this barebox:/ md -l 0xa0000003+4 a0000003: Ooops, address error on load or ifetch! ... ### ERROR ### Please RESET the board ### Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: import exception registers restoring macros from linux kernelAntony Pavlov2015-11-111-0/+87
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: avoid excessive exceptionAntony Pavlov2015-11-111-1/+1
| | | | | | | | | This commit clears ERL (ERror Level) flag on start. If this flag is set then we get 'TLB miss on load or ifetch' just after return from exception. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mips'Sascha Hauer2015-11-061-0/+32
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| * MIPS: ath79: add pbl_ar9331_uart_enable macroAntony Pavlov2015-11-031-0/+11
| | | | | | | | | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * MIPS: ath79: add pbl_ar9331_pll macroOleksij Rempel2015-11-031-0/+21
| | | | | | | | | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | rework remap_rangeSascha Hauer2015-11-031-13/+1
|/ | | | | | | | | | | | | | | | | | remap_range is for remapping regions with different cache attributes. It is implemented for ARM and PowerPC only, the other architectures only provide stubs. Currently the new cache attributes are passed in an architecture specific way and the attributes have to be retrieved by calls to mmu_get_pte_cached_flags() and mmu_get_pte_uncached_flags(). Make this simpler by providing architecture independent flags which can be directly passed to remap_range() Also provide a MAP_ARCH_DEFAULT flag and a arch_can_remap() function. The MAP_ARCH_DEFAULT defaults to whatever caching type the architecture has as default. the arch_can_remap() function returns true if the architecture can change the cache attributes, false otherwise. This allows the memtest code to better find out what it has to do. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* gpio: Drop asm-generic/gpio.hSascha Hauer2015-08-201-6/+0
| | | | | | | | | | Since we no longer have custom gpio function prototypes we can drop the prototypes from asm-generic/gpio.h can add them to include/gpio.h instead. While at it add static inline dummy wrappers for !CONFIG_GENERIC_GPIO so that code using gpios can compile without gpio support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/posix_types'Sascha Hauer2015-06-093-144/+2
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| * mips: use generic posix_types.hSascha Hauer2015-06-031-129/+1
| | | | | | | | | | | | | | Use generic asm-generic/posix_types.h instead of repeating the typedefs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * drop __BITS_PER_LONGSascha Hauer2015-05-221-3/+1
| | | | | | | | | | | | | | | | | | The kernel has __BITS_PER_LONG and BITS_PER_LONG. The formaer is needed for architectures which support 32bit userspace on a 64bit kernel. This is not relevant for barebox, so drop __BITS_PER_LONG and use BITS_PER_LONG only. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * dma: Use generic place for dma_addr_t typedefSascha Hauer2015-05-221-12/+0
| | | | | | | | | | | | | | | | | | Instead of letting all architectures define their own dma_addr_t use a common place in include/linux/types.h and use a Kconfig symbol that architectures can select to define the width of dma_addr_t. The same is done in the Kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | MIPS: asm/debug_ll_ns16550.h: use plain inline instead of __inline__Antony Pavlov2015-06-041-1/+1
|/ | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: debug_ll_ns16550.h: drop _ns16550 suffixAntony Pavlov2015-05-052-21/+20
| | | | | | | | | | | | | This commit makes it possible to have unified debug_ll_* assembler routines for differrent UART program model. E.g. we can use debug_ll_putc() routine in common code without knowledge on exact UART model: ns16550 or ar933x. Also rename *_check_char -> *_tstc. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: change dma_alloc/free_coherent to common prototypesLucas Stach2015-03-062-3/+5
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: qemu-malta: add little-endian mode supportAntony Pavlov2014-10-101-0/+7
| | | | | | | | | | | | | | | | | We can't just enable SYS_SUPPORTS_LITTLE_ENDIAN for successful little-endian qemu-malta barebox build. Some byte swapping-related macros are missed, e.g.: arch/mips/mach-malta/pci.c: In function 'pcibios_init': arch/mips/mach-malta/pci.c:218:28: error: 'GT_PCI0_CMD_MBYTESWAP_BIT' undeclared (first use in this function) GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | ^ This patch adds necessary macros definition. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add (another) Ingenic vendor IDAntony Pavlov2014-09-111-0/+1
| | | | | | | | | | | | | | | | | | | The latest Ingenic CPUs (e.g. JZ4780) use new vendor ID. Based on commit from https://github.com/MIPS/CI20_linux/tree/ci20-v3.16 commit 00b672aa52f299f1d67ab18274c3f5e5d5a15767 Author: Paul Burton <paul.burton@imgtec.com> Date: Mon Jul 8 12:14:28 2013 +0100 MIPS: add (another) Ingenic vendor ID Ingenic have switched to a new vendor ID for the Xburst core used in their current SoCs such as the jz4780. Add this vendor ID and handle it in addition to their former vendor ID. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* consistently use the same bitops.h fileSascha Hauer2014-07-171-11/+15
| | | | | | | | | | | | | | | | We have many variants of the same bitops.h file. Consistently use the same file for all architectures which completely use the generic bitops versions. Some architectures had static inline versions of functions identically to the generic versions, these are removed and the generic versions are used directly now. Also several architectures depend on the generic find_*_bit functions but didn't have the GENERIC_FIND_NEXT_BIT Kconfig option selected. This is added where needed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add PCI support for GT64120-based Malta boardAntony Pavlov2014-07-041-0/+53
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add dma_alloc_coherent()Antony Pavlov2014-07-041-0/+25
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add <asm/gpio.h> header fileAntony Pavlov2014-06-241-0/+6
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: io: include generic io.hSascha Hauer2014-04-091-0/+2
| | | | | | | To get definitions for inb/outb and friends. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Antony Pavlov <antonynpavlov@gmail.com>
* common: Allow for I/O mapped I/OMichel Stam2014-04-081-0/+2
| | | | | | | | Rework the current framework so that I/O mapped I/O resources are also possible. Signed-off-by: Michel Stam <michel@reverze.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: mach-xburst: fix DEBUG_LL=n build errorAntony Pavlov2014-03-281-0/+2
| | | | | | | | | | | | | | | | | Here is my error log: CC common/startup.o In file included from arch/mips/mach-xburst/include/mach/debug_ll.h:25, from include/debug_ll.h:31, from common/startup.c:36: arch/mips/include/asm/debug_ll_ns16550.h: In function 'PUTC_LL': arch/mips/include/asm/debug_ll_ns16550.h:62: error: 'DEBUG_LL_UART_ADDR' undeclared (first use in this function) arch/mips/include/asm/debug_ll_ns16550.h:62: error: (Each undeclared identifier is reported only once arch/mips/include/asm/debug_ll_ns16550.h:62: error: for each function it appears in.) make[1]: *** [common/startup.o] Error 1 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add Loongson-1B processor constants and CPU probeAntony Pavlov2014-01-211-0/+27
| | | | | | | | | | | | | | | | | | | | | | This commit is based on this linux commit: commit 2fa36399e63c911134f28b6878aada9b395c4209 Author: Kelvin Cheung <keguang.zhang@gmail.com> Date: Wed Jun 20 20:05:32 2012 +0100 MIPS: Add CPU support for Loongson1B Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT) and the Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. [ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device which also is why it identifies itself with the Legacy Vendor ID in the PrID register. When applying the patch I shoveled some code around to keep things in alphabetical order and avoid forward declarations.] Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips asm/types.h: add #ifndef to fix compile errorDu Huanpeng2014-01-061-0/+4
| | | | | | | | without "#ifndef __ASSEMBLY__ #endif", an assembly file including this file will break compilation. Signed-off-by: Du Huanpeng <u74147@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: import exception registers saving from linux kernelAntony Pavlov2013-12-041-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking registers saving: $ make qemu-malta_defconfig $ make ... $ qemu-system-mips -nodefaults -M malta -m 256 \ -nographic -serial stdio -bios ./barebox-flash-image ... barebox:/ md -l 0x03 Ooops, address error on load or ifetch! $ 0 : 00000000 00000000 ffffffff 0000003f $ 4 : 00000000 ffffffff 00000004 00000004 $ 8 : 00000003 a0404d50 00000001 00000002 $12 : a0404d50 0000000a a0840000 00000003 $16 : 00000100 a0404d50 00000100 00000003 $20 : 00000000 a0406cd8 00000000 00000000 $24 : a083b4d8 a083058c $28 : 00000000 a03ffca8 a0406ab0 a0830604 Hi : 00000000 Lo : 00000040 epc : a083056c ra : a0830604 Status: 00000006 Cause : 00000410 Config: 80008482 ### ERROR ### Please RESET the board ### Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add asm-offsets.h generationAntony Pavlov2013-12-042-0/+36
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: qemu-malta: use YAMON-style GT64120 memory mapAntony Pavlov2013-10-281-0/+37
| | | | | | | | | | | | | There are some reasons for using YAMON-style memory map: * we can run Linux kernel from barebox; * we can use GXemul for running barebox. YAMON-style GT64120 memory map make move UART to the new position. The files gt64120.h and mach-gt64120.h are imported from Linux. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add nmon MIPS nano-monitorAntony Pavlov2013-06-252-6/+364
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nmon is a tiny monitor (<1200 bytes) program for the MIPS processors. It can operate with NO working RAM at all! It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging. With no changes nmon should work on different MIPS processors as it uses only common MIPS-I instructions. nmon is inspired by mmon, MIPS VR4300 Mini-monitor. mmon is copyrighted 1996, 2003 by Eric Smith. Also Alexander Voropay must be noted for his work on qemu & YAMON mmon adaptations made in 2006 and 2007. See http://www.brouhaha.com/~eric/software/mmon/ for mmon details. The mmon's features missed in nmon: * batch memory dumps; * byte and 16-bit half-words dumps and stores; * fill memory; * load S-records (this function make sense only if RAM works properly). nmon has only 4 commands: q - quit to barebox d <addr> - read 32-bit word from <addr> address w <addr> <val> - write 32-bit word <val> to <addr> g <addr> - jump to <addr> Addresses and data must be given in hexadecimal. Everything (including hex digits 'a'..'f') must be in lower case. EXAMPLE: change value of word with address 0xa0000000 nmon> d a0000000 00000000 nmon> w a0000000 12345678 nmon> d a0000000 12345678 nmon> There is no error checking of any kind. If you give an invalid address you will probably get an exception which will hang the board and you will have to press the reset button. You can interrupt current command (e.g. you have made error in input <addr> value) by pressing the <ESC> key. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add pbl_probe_mem macroOleksij Rempel2013-06-211-0/+12
| | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add pbl_sleep macroOleksij Rempel2013-06-211-0/+10
| | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add mips_barebox_10h asm macroAntony Pavlov2013-06-211-0/+16
| | | | | | | | | The mips_barebox_10h macro inserts at offset 0x10 of the barebox image the string 'barebox ' followed by compile time version mark. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: use generated label in ADR macroAntony Pavlov2013-06-181-2/+2
| | | | | | | | | | | | | The generated label usage make possible to use the ADR macro many times. If we don't use a generated label and we try to use the ADR macro second time then we get Error: symbol `_pc' is already defined Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: remove extra LONGSIZE definitionAntony Pavlov2013-06-181-2/+0
| | | | | | | We already have the LONGSIZE macro definition in <asm/asm.h>. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: unify ns16550 debug_ll support codeAntony Pavlov2013-06-042-37/+15
| | | | | | | | | | | This commit moves the C debug_ll code from the MIPS <debug_ll_ns16550.h> header file to the MIPS <asm/debug_ll_ns16550.h> header file, so the C code and the asm code can use the same register address macros. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add low-level debug asm macros for ns16550Antony Pavlov2013-06-021-0/+100
| | | | | | | | | This patch adds macros for ns16550 port initialisation and single char output. The macros can be used in MIPS asm pbl code. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: asm/mipsregs.h: remove unused stuffAntony Pavlov2013-05-311-8/+0
| | | | | | | | In barebox we have no CONFIG_MIPS_MT_SMTC Kconfig option. So remove the code under this macro. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2013-02-041-0/+18
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| * remap_range: make function 'remap_range' globalAlexander Aring2013-01-181-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Change function remap_range in arm architecture to make it global accessable. For example command 'memtest' can change pte flags to enable or disable cache. Add dummy function for others architectures that doesn't have mmu or pte support. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | MIPS: introduce ram0 regions register functionAntony Pavlov2013-01-271-0/+12
|/ | | | | | | | | | | | | | On MIPS there are two segments in CPU address space that can be used for untranslated memory access: KSEG0 and KSEG1. KSEG0 is used for cached access and KSEG1 is used for uncached one. The instroduced mips_add_ram0() function registers two address regions for memory access: one in KSEG0 and the other one in KSEG1. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add pre-bootloader (pbl) image supportAntony Pavlov2012-12-141-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on ARM pbl support and allows creating a pre-bootloader binary for compressed image. For different MIPS SoCs (or even for different boards based on the same SoC) the operations carried on in start-pbl.S can be very different. The additional constraints can be imposed on the size of the boot code or the special magic labels in the beginning of the boot code; In some cases it could be necessary to show CPU is alive as early as possible (transmit a char via UART or blink a LED). So the demands for pbl start operation can be very different. E.g. malta board store boot code at the NOR flash mapped to the MIPS power-on address (0xbfc00000); it is the most simple case: we need just copy pbl image from direct-mapped flash to RAM and jump there. The XBurst-powered boards store boot code in the beginning of a NAND flash or in the beginning of SD/MMC card. In this case we must use simple and short NAND or SD/MMC access routines to copy pbl image to RAM. To meet so different demands a simple technique is selected: * MIPS pbl entry point located in file arch/mips/boot/start-pbl.S. * MIPS pbl code (see start-pbl.S) assumes that every pbl-enabled board has a arch/mips/boards/<BOARD>/include/board/board_pbl_start.h header file. This file must contain definition of the board_pbl_start macro. This macro is used as start of pbl image; * the most popular asm routines (stack setup, relocation to link address, NS16550 initialization (WIP) and so on) are containt in the arch/mips/include/asm/pbl_macros.h header file. So board pbl macro can use it if necessary. It is possible to create similar headers with macros for each specific SoC; so even if we have many different boards based on the same SoC the board_pbl_start macro for every board can be short and clear. * after board-specific initialization the stack pointer is initialized and pbl C code is started. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* debug_ll: Let architectures define PUTC_LL directlySascha Hauer2012-12-051-1/+1
| | | | | | | | putc already is a regular barebox function. To avoid conflicts and confusions just let architectures define PUTC_LL directly instead of going through this addiotional redirection. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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