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* MIPS: add PCI support for GT64120-based Malta boardAntony Pavlov2014-07-041-0/+53
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add dma_alloc_coherent()Antony Pavlov2014-07-041-0/+25
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add <asm/gpio.h> header fileAntony Pavlov2014-06-241-0/+6
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: io: include generic io.hSascha Hauer2014-04-091-0/+2
| | | | | | | To get definitions for inb/outb and friends. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Antony Pavlov <antonynpavlov@gmail.com>
* common: Allow for I/O mapped I/OMichel Stam2014-04-081-0/+2
| | | | | | | | Rework the current framework so that I/O mapped I/O resources are also possible. Signed-off-by: Michel Stam <michel@reverze.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: mach-xburst: fix DEBUG_LL=n build errorAntony Pavlov2014-03-281-0/+2
| | | | | | | | | | | | | | | | | Here is my error log: CC common/startup.o In file included from arch/mips/mach-xburst/include/mach/debug_ll.h:25, from include/debug_ll.h:31, from common/startup.c:36: arch/mips/include/asm/debug_ll_ns16550.h: In function 'PUTC_LL': arch/mips/include/asm/debug_ll_ns16550.h:62: error: 'DEBUG_LL_UART_ADDR' undeclared (first use in this function) arch/mips/include/asm/debug_ll_ns16550.h:62: error: (Each undeclared identifier is reported only once arch/mips/include/asm/debug_ll_ns16550.h:62: error: for each function it appears in.) make[1]: *** [common/startup.o] Error 1 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add Loongson-1B processor constants and CPU probeAntony Pavlov2014-01-211-0/+27
| | | | | | | | | | | | | | | | | | | | | | This commit is based on this linux commit: commit 2fa36399e63c911134f28b6878aada9b395c4209 Author: Kelvin Cheung <keguang.zhang@gmail.com> Date: Wed Jun 20 20:05:32 2012 +0100 MIPS: Add CPU support for Loongson1B Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT) and the Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. [ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device which also is why it identifies itself with the Legacy Vendor ID in the PrID register. When applying the patch I shoveled some code around to keep things in alphabetical order and avoid forward declarations.] Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips asm/types.h: add #ifndef to fix compile errorDu Huanpeng2014-01-061-0/+4
| | | | | | | | without "#ifndef __ASSEMBLY__ #endif", an assembly file including this file will break compilation. Signed-off-by: Du Huanpeng <u74147@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: import exception registers saving from linux kernelAntony Pavlov2013-12-041-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking registers saving: $ make qemu-malta_defconfig $ make ... $ qemu-system-mips -nodefaults -M malta -m 256 \ -nographic -serial stdio -bios ./barebox-flash-image ... barebox:/ md -l 0x03 Ooops, address error on load or ifetch! $ 0 : 00000000 00000000 ffffffff 0000003f $ 4 : 00000000 ffffffff 00000004 00000004 $ 8 : 00000003 a0404d50 00000001 00000002 $12 : a0404d50 0000000a a0840000 00000003 $16 : 00000100 a0404d50 00000100 00000003 $20 : 00000000 a0406cd8 00000000 00000000 $24 : a083b4d8 a083058c $28 : 00000000 a03ffca8 a0406ab0 a0830604 Hi : 00000000 Lo : 00000040 epc : a083056c ra : a0830604 Status: 00000006 Cause : 00000410 Config: 80008482 ### ERROR ### Please RESET the board ### Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add asm-offsets.h generationAntony Pavlov2013-12-042-0/+36
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: qemu-malta: use YAMON-style GT64120 memory mapAntony Pavlov2013-10-281-0/+37
| | | | | | | | | | | | | There are some reasons for using YAMON-style memory map: * we can run Linux kernel from barebox; * we can use GXemul for running barebox. YAMON-style GT64120 memory map make move UART to the new position. The files gt64120.h and mach-gt64120.h are imported from Linux. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add nmon MIPS nano-monitorAntony Pavlov2013-06-252-6/+364
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nmon is a tiny monitor (<1200 bytes) program for the MIPS processors. It can operate with NO working RAM at all! It uses only the processor registers and NS16550-compatible UART port for operation, so it can be used for a memory controller setup code debugging. With no changes nmon should work on different MIPS processors as it uses only common MIPS-I instructions. nmon is inspired by mmon, MIPS VR4300 Mini-monitor. mmon is copyrighted 1996, 2003 by Eric Smith. Also Alexander Voropay must be noted for his work on qemu & YAMON mmon adaptations made in 2006 and 2007. See http://www.brouhaha.com/~eric/software/mmon/ for mmon details. The mmon's features missed in nmon: * batch memory dumps; * byte and 16-bit half-words dumps and stores; * fill memory; * load S-records (this function make sense only if RAM works properly). nmon has only 4 commands: q - quit to barebox d <addr> - read 32-bit word from <addr> address w <addr> <val> - write 32-bit word <val> to <addr> g <addr> - jump to <addr> Addresses and data must be given in hexadecimal. Everything (including hex digits 'a'..'f') must be in lower case. EXAMPLE: change value of word with address 0xa0000000 nmon> d a0000000 00000000 nmon> w a0000000 12345678 nmon> d a0000000 12345678 nmon> There is no error checking of any kind. If you give an invalid address you will probably get an exception which will hang the board and you will have to press the reset button. You can interrupt current command (e.g. you have made error in input <addr> value) by pressing the <ESC> key. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add pbl_probe_mem macroOleksij Rempel2013-06-211-0/+12
| | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add pbl_sleep macroOleksij Rempel2013-06-211-0/+10
| | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add mips_barebox_10h asm macroAntony Pavlov2013-06-211-0/+16
| | | | | | | | | The mips_barebox_10h macro inserts at offset 0x10 of the barebox image the string 'barebox ' followed by compile time version mark. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: use generated label in ADR macroAntony Pavlov2013-06-181-2/+2
| | | | | | | | | | | | | The generated label usage make possible to use the ADR macro many times. If we don't use a generated label and we try to use the ADR macro second time then we get Error: symbol `_pc' is already defined Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: remove extra LONGSIZE definitionAntony Pavlov2013-06-181-2/+0
| | | | | | | We already have the LONGSIZE macro definition in <asm/asm.h>. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: unify ns16550 debug_ll support codeAntony Pavlov2013-06-042-37/+15
| | | | | | | | | | | This commit moves the C debug_ll code from the MIPS <debug_ll_ns16550.h> header file to the MIPS <asm/debug_ll_ns16550.h> header file, so the C code and the asm code can use the same register address macros. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: pbl: add low-level debug asm macros for ns16550Antony Pavlov2013-06-021-0/+100
| | | | | | | | | This patch adds macros for ns16550 port initialisation and single char output. The macros can be used in MIPS asm pbl code. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: asm/mipsregs.h: remove unused stuffAntony Pavlov2013-05-311-8/+0
| | | | | | | | In barebox we have no CONFIG_MIPS_MT_SMTC Kconfig option. So remove the code under this macro. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2013-02-041-0/+18
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| * remap_range: make function 'remap_range' globalAlexander Aring2013-01-181-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Change function remap_range in arm architecture to make it global accessable. For example command 'memtest' can change pte flags to enable or disable cache. Add dummy function for others architectures that doesn't have mmu or pte support. Signed-off-by: Alexander Aring <alex.aring@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | MIPS: introduce ram0 regions register functionAntony Pavlov2013-01-271-0/+12
|/ | | | | | | | | | | | | | On MIPS there are two segments in CPU address space that can be used for untranslated memory access: KSEG0 and KSEG1. KSEG0 is used for cached access and KSEG1 is used for uncached one. The instroduced mips_add_ram0() function registers two address regions for memory access: one in KSEG0 and the other one in KSEG1. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add pre-bootloader (pbl) image supportAntony Pavlov2012-12-141-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on ARM pbl support and allows creating a pre-bootloader binary for compressed image. For different MIPS SoCs (or even for different boards based on the same SoC) the operations carried on in start-pbl.S can be very different. The additional constraints can be imposed on the size of the boot code or the special magic labels in the beginning of the boot code; In some cases it could be necessary to show CPU is alive as early as possible (transmit a char via UART or blink a LED). So the demands for pbl start operation can be very different. E.g. malta board store boot code at the NOR flash mapped to the MIPS power-on address (0xbfc00000); it is the most simple case: we need just copy pbl image from direct-mapped flash to RAM and jump there. The XBurst-powered boards store boot code in the beginning of a NAND flash or in the beginning of SD/MMC card. In this case we must use simple and short NAND or SD/MMC access routines to copy pbl image to RAM. To meet so different demands a simple technique is selected: * MIPS pbl entry point located in file arch/mips/boot/start-pbl.S. * MIPS pbl code (see start-pbl.S) assumes that every pbl-enabled board has a arch/mips/boards/<BOARD>/include/board/board_pbl_start.h header file. This file must contain definition of the board_pbl_start macro. This macro is used as start of pbl image; * the most popular asm routines (stack setup, relocation to link address, NS16550 initialization (WIP) and so on) are containt in the arch/mips/include/asm/pbl_macros.h header file. So board pbl macro can use it if necessary. It is possible to create similar headers with macros for each specific SoC; so even if we have many different boards based on the same SoC the board_pbl_start macro for every board can be short and clear. * after board-specific initialization the stack pointer is initialized and pbl C code is started. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* debug_ll: Let architectures define PUTC_LL directlySascha Hauer2012-12-051-1/+1
| | | | | | | | putc already is a regular barebox function. To avoid conflicts and confusions just let architectures define PUTC_LL directly instead of going through this addiotional redirection. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: remove unused variableSascha Hauer2012-10-171-3/+0
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Treewide: remove address of the Free Software FoundationSascha Hauer2012-09-176-23/+0
| | | | | | | The FSF address has changed in the past. Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: remove undefined local_irq_save/local_irq_restoreSascha Hauer2012-09-161-4/+0
| | | | | | | | mips currently uses local_irq_save and local_irq_restore which are not defined. Drop them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Antony Pavlov <antonynpavlov@gmail.com>
* MIPS: add initial exceptions handlingAntony Pavlov2012-07-271-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | Checking exception handling: $ make qemu-malta_defconfig $ make ... $ qemu-system-mips -nodefaults -M malta -m 256 \ -nographic -serial stdio -bios ./barebox.bin ... barebox:/ md -l 0x03 Ooops, address error on load or ifetch! EPC = 0xa082783c CP0_STATUS = 0x00000006 CP0_CAUSE = 0x00000410 CP0_CONFIG = 0x80008482 ### ERROR ### Please RESET the board ### Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: remove unused processor-specific constants and macrosAntony Pavlov2012-07-092-40/+0
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/dma-cache-align'Sascha Hauer2012-07-021-0/+13
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| * blackfin, mips, openrisc, ppc, sandbox, x86: add generic dma_alloc, dma_free ↵Marc Kleine-Budde2012-06-301-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | inlines Some drivers call dma_inv_range() on buffers, on arm these buffers must be cache line aligned. This patch introduces a generic dma_alloc, dma_free. Archs can implement in their own functions in "asm/dma.h" and add a: #define dma_alloc dma_alloc #define dma_free dma_free On all other archs the generic versions, which translate into xmalloc and free are used. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mips: Add missing ffs and fls includeSascha Hauer2012-06-281-0/+3
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: import CPU and cache detection code from Linux 3.4Antony Pavlov2012-05-234-1/+469
| | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add common header file for DEBUG_LL via NS16550Antony Pavlov2012-05-131-0/+40
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: add in_be16/32 and out_be16/32 for cfi supportJean-Christophe PLAGNIOL-VILLARD2012-04-301-0/+5
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* MIPS: import header filesAntony Pavlov2011-08-0513-0/+1945
| | | | | | | | | | | | from linux-2.6.39: * arch/mips/include/asm/* * include/asm-generic/int-ll64.h from barebox-2011.07.0 arch/x86: * arch/mips/include/asm/sections.h Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: initial commit: add empty but required header filesAntony Pavlov2011-08-055-0/+140
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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