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* MIPS: relocation: do not use configurable memory layoutOleksij Rempel2019-04-231-0/+14
| | | | | | | | | The relocator is not able to patch properly new location of the stack. To make it work properly it is better to disable HAVE_CONFIGURABLE_MEMORY_LAYOUT. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: migrate all files to SPDXOleksij Rempel2019-01-031-5/+1
| | | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Roland Hieber <r.hieber@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add 74Kc infoOleksij Rempel2017-07-311-0/+4
| | | | | | | This patch is preparation for SoC QCA AR9344 Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* mips: c-r4k: detect secondary cachePeter Mamonov2015-11-031-2/+0
| | | | | Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add (another) Ingenic vendor IDAntony Pavlov2014-09-111-0/+1
| | | | | | | | | | | | | | | | | | | The latest Ingenic CPUs (e.g. JZ4780) use new vendor ID. Based on commit from https://github.com/MIPS/CI20_linux/tree/ci20-v3.16 commit 00b672aa52f299f1d67ab18274c3f5e5d5a15767 Author: Paul Burton <paul.burton@imgtec.com> Date: Mon Jul 8 12:14:28 2013 +0100 MIPS: add (another) Ingenic vendor ID Ingenic have switched to a new vendor ID for the Xburst core used in their current SoCs such as the jz4780. Add this vendor ID and handle it in addition to their former vendor ID. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: add Loongson-1B processor constants and CPU probeAntony Pavlov2014-01-211-0/+21
| | | | | | | | | | | | | | | | | | | | | | This commit is based on this linux commit: commit 2fa36399e63c911134f28b6878aada9b395c4209 Author: Kelvin Cheung <keguang.zhang@gmail.com> Date: Wed Jun 20 20:05:32 2012 +0100 MIPS: Add CPU support for Loongson1B Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT) and the Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. [ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device which also is why it identifies itself with the Legacy Vendor ID in the PrID register. When applying the patch I shoveled some code around to keep things in alphabetical order and avoid forward declarations.] Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: import CPU and cache detection code from Linux 3.4Antony Pavlov2012-05-231-0/+143
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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