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* MIPS: add generic device tree 2nd stage supportAntony Pavlov2024-03-131-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building and running barebox for 32-bit malta: export ARCH=mips export CROSS_COMPILE=mips-linux-gnu- make -s qemu-malta_defconfig sed -i "s/# \(CONFIG_BOARD_MIPS_GENERIC_DT\) is not set/\1=y/" .config make -s oldconfig make -s qemu-system-mips -M malta -cpu 24Kf -m 256M \ -nographic -serial mon:stdio \ -bios images/barebox-qemu-malta.img \ -net user,tftp=$(pwd) -net nic,model=e1000 Building and running barebox for 64-bit malta: export ARCH=mips export CROSS_COMPILE=mips-linux-gnu- make -s qemu-malta64el_defconfig sed -i "s/# \(CONFIG_BOARD_MIPS_GENERIC_DT\) is not set/\1=y/" .config make -s oldconfig make -s qemu-system-mips64el -M malta -cpu MIPS64R2-generic -m 256M \ -nographic -serial mon:stdio \ -bios images/barebox-qemu-malta.img.swapped \ -net user,tftp=$(pwd) -net nic,model=e1000 Use bootm to run barebox-dt-2nd.img (external device tree): barebox@qemu malta:/ dhcp barebox@qemu malta:/ cp /mnt/tftp/images/barebox-dt-2nd.img barebox.img barebox@qemu malta:/ cp /mnt/tftp/arch/mips/dts/qemu-malta.dtb . barebox@qemu malta:/ imd barebox.img barebox@qemu malta:/ bootm -o qemu-malta.dtb barebox.img Use bootm to run barebox-qemu-malta.img (encapsulated device tree): barebox@qemu malta:/ dhcp barebox@qemu malta:/ cp /mnt/tftp/images/barebox-qemu-malta.img barebox.img barebox@qemu malta:/ imd barebox.img barebox@qemu malta:/ bootm barebox.img N.B. Use just the same commands for both 32-bit and 64-bit malta boards. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20240310215434.1220451-1-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: bootm: fix format string type mismatchAhmad Fatoum2023-09-121-1/+1
| | | | | | | | data->of_root_node is a pointer, so print it with 0x%p. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230912095809.287289-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: reloc: use IS_ALIGNED macro to check for an alignmentDenis Orlov2023-07-271-1/+1
| | | | | | | | Improves the code readability a tiny little bit. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-22-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: c-r4k: remove extra function declarationDenis Orlov2023-07-271-2/+0
| | | | | | | | | 'r4k_cache_init()' is already declared in the appropriate 'asm/cache.h' header. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-21-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: c-r4k: do flush secondary cacheDenis Orlov2023-07-271-6/+6
| | | | | | | | | | | | | | Even though we probe for the secondary cache, we don't actually utilize it when flushing. It seems that the reason for this is that no MIPS board currently supported in barebox actually has secondary caches and thus requires the additional logic in handling them. Add the required functions and calls to them. This will make it easier to add support for boards that do happen to have secondary caches. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-20-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: c-r4k: generate blast_*cache functions via macrosDenis Orlov2023-07-271-17/+24
| | | | | | | | | | This gets us rid of this logic repeated in 'flush_cache_all()' for each cache and allows to use blast_*cache funcs elsewhere if such a need arises. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-19-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: c-r4k: prettify code in __BUILD_BLAST_CACHE_RANGEDenis Orlov2023-07-271-8/+5
| | | | | | | | | | | Even though the original code was taken from Linux, it is quite old and crufty. Replace the 'while (1)' loop with the 'for' one, use const for constant variables and use ALIGN_DOWN macro instead of repeating its code. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-18-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: main_entry: remove exception vector arrayDenis Orlov2023-07-271-21/+8
| | | | | | | | | | | | | | | | | | | | This code must have been taken from Linux, where such a mechanism allows for an efficient exception vector replacement for board-specific code. We don't really need that. If some extensions for exception vector are to be required, this may be done inside the generic handler code anyway. As we are not using this code, it seems reasonable to just remove it. Also properly calculate the size of the handler that we are copying into the designated vectors. Originally, we just made a copy of a fixed size, copying more than actually needed. We could have just hardcoded this value there, as the code to copy now consists of just two instructions. However it feels more safe to calculate that in code instead, so that we don't have to update this value if some code is added there in the future. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-17-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: print BadVAddr CP0 register on exceptionDenis Orlov2023-07-271-1/+2
| | | | | | | | | This register contains the failing address on Address Error and some TLB-related exceptions, and is useful for debugging purposes. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-8-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: cpuinfo: use appropriate format specifiers in printfDenis Orlov2023-07-271-3/+3
| | | | | | Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-7-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: reloc: mark relocate_code() as noreturnDenis Orlov2023-07-271-2/+2
| | | | | | | | | | After relocating the code we jump straight to it, with the function having an 'unreachable()' call at the end. So add an appropriate attribute. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-6-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: barebox.lds: remove extra whitespaceDenis Orlov2023-07-271-2/+0
| | | | | | Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230725050618.3451-5-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mips'Sascha Hauer2023-06-225-38/+64
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| * MIPS: make setjmp/longjmp/initjmp available in 64BIT buildsDenis Orlov2023-06-091-24/+24
| | | | | | | | | | | | | | | | | | | | Make the code compatible with 64-bit configurations by storing saved register values with unsigned long type and using generic macros in assembly code. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230605202634.42175-17-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * MIPS: add 64-bit support for optimized string functionsDenis Orlov2023-06-091-5/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds macro definitions and a bit of code that allow to properly utilise doubleword instructions on mips64. These changes are taken directly from Linux sources. Also switch some o32-specific register definitions to generic ones for this code to actually compile for n64 ABI. While at it, this also removes an unused macro define. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230605202634.42175-16-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * MIPS: traps: fix passing wrong sp when returning from exceptionDenis Orlov2023-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code seems to have been working on 32-bit builds by accident. However it totally broke on 64 bits, resulting in "restoring" some garbage into registers. The reason the code worked on 32 bits is this. When we are entering the barebox_exc_handler() function, we are passing in a register the current stack pointer as an argument (which corresponds to the regs parameter). On o32 ABI the space for arguments passed in registers is reserved on the stack by the caller. So, when we are taking the address of regs in the body of the function, we have to put this argument on the stack, into the first reserved slot. However, this slot is located exactly at the current 'sp' and thus the address of regs happens to be the same as its value! On n64 ABI, however, the arguments passed in registers are saved onto the stack on the callee side, so we end up with the wrong value being used as the stack pointer. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230605202634.42175-14-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * MIPS: use MIPS32/MIPS64 generic instruction macrosDenis Orlov2023-06-091-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use PTR_* for various arithmetic operations on pointers, and also use PTR_LA instead of simple 'la' instruction, as it will correctly handle loading 64-bit addresses from non-32-bit-compatible virtual memory segments. This fixes "la used to load 64-bit address; recommend using dla instead" warnings when compiling assembly code with CONFIG_64BIT. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230605202634.42175-8-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * MIPS: reloc: fix relocation with CONFIG_64BIT enabledDenis Orlov2023-06-091-4/+3
| | | | | | | | | | | | | | | | | | | | | | Use CKSEG instead of KSEG, allowing it to compile on 64BIT configurations. Also make sure that we do not truncate target relocation address by writing it into a 32-bit wide variable. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Reviewd-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230605202634.42175-4-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | dma: rework dma_sync_single_for_*() interfaceDenis Orlov2023-06-061-9/+9
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Currently, a lot of code handles dma_addr_t values as if they actually hold CPU addresses. However, this is not always true. For example, MIPS architecture requires an explicit conversion from the physical address space to some virtual address space segment to get a valid CPU-side pointer. Another issue is that DMA ranges that may be specified in a device tree will not work this way. To get from a virtual address to a dma handle and vice versa we need to add/subtract some offset, which is calculated from "dma-ranges" property. Only dma_map_single() was doing this, but dma_sync_single_for_*() also should. Improve the interface by adding 'struct device' as the first argument to the dma_sync_single_for_*(). This allows to do cpu_to_dma/dma_to_cpu() conversions in common code and call into arch-specific code with proper cpu-side addresses. To make things more clear, make the virtual address argument of those arch-side functions be properly represented with a void* type. Apply the required changes in device drivers that use the affected functions, making them pass the appropriate device pointer. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230604215002.20240-2-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: bootm: remove unnecessary phys/virt conversionsDenis Orlov2023-03-161-2/+2
| | | | | | | | | They are not doing anything there - we should already have proper virtual addresses represented by those pointers. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230315085953.4094660-4-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: bootm: do not leak memory on error in of_overlay_load_firmware()Denis Orlov2023-03-161-1/+1
| | | | | | Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230315085953.4094660-3-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: bootm: do not free fdt pointer that contains an errorDenis Orlov2023-03-161-2/+2
| | | | | | | | Also add a proper error message. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230315085953.4094660-2-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: dma-default: do not flush caches in dma_sync_single_* excessivelyDenis Orlov2023-03-141-19/+17
| | | | | | | | | | | | | | | | Change the logic to be different depending on whether we are doing synchronization for a cpu or a device. This gets rid of unnecessary cache flushing in some cases. While at it, also simplify code a bit, collapsing two cases with the same code in a switch statement in dma_sync_single_for_device(). The functional change itself is taken from Linux commit 'MIPS: make dma_sync_*_for_cpu a little less overzealous' (hash: cbf1449ba5aec9cf4c68b69f899391a8d42e9b8f). Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230313105308.3108127-4-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: dma-default: use virtual addresses when flushing cachesDenis Orlov2023-03-141-2/+6
| | | | | | | | | | | Cache flushing functions expect virtual addresses, so make sure those are properly converted from the physical ones in dma_sync_single_for_*. QEMU doesn't care as it ignores cache instructions, but without such change this code would result in TLB exceptions on real hardware. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230313105308.3108127-3-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: dma: remove unnecessary ifdefsDenis Orlov2023-02-131-8/+0
| | | | | | | | | We do not support any MIPS CPUs that are not MIPS32/MIPS64, so there is no reason to check for those. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20230210144745.915720-3-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: rename CONFIG_HAS_ARCH_SJLJ to CONFIG_ARCH_HAS_SJLJAhmad Fatoum2022-12-071-1/+1
| | | | | | | | | We have 9 symbols beginning with ARCH_HAS, but only with HAS_ARCH. Change it over for symmetry. No functional change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221205133033.3008535-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: move OUTPUT_FORMAT/ARCH definition into headerAhmad Fatoum2022-10-112-2/+2
| | | | | | | | | | In order to allow us having architecture-indepenent linker scripts, move the definition for the format and the architecture into the new <asm/barebox.lds.h> header file. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221010061122.2084009-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: introduce <asm/barebox.lds.h>Ahmad Fatoum2022-10-112-2/+2
| | | | | | | | | | | | | | We have a separate linker script for each architecture and one more for PBL if supported. All linker scripts include <asm-generic/barebox.lds.h>. In future, we may want to use a linker script common to more than one architecture. Prepare for this by having each architecture define a <asm/barebox.lds.h>. Currently, these files contain little more than 1-2 #include directives, but this will change in later commits. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20221010061122.2084009-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pbl: replace __piggydata_end with __image_endAhmad Fatoum2022-08-221-1/+2
| | | | | | | | | | | | | | | __piggydata_end and __image_end used to be synonyms before the addition of external firmware. Now that external firmware is located after __piggydata_end, code using it needs to be revisited. There's no reason to have code reference __piggydata_end. Either they want all the rest of the image, so they should use __image_end instead or they want just the piggy data, in which case they can read the data size embedded into the piggydata itself. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220818050447.2072932-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clocksource: assign non-zero priorities to all clocksourcesAhmad Fatoum2022-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most barebox clocksources have a zero priority and if multiple of them exist, but no higher priority ones, the first to call init_clock wins. Some supported boards like the Raspberry Pi additionally depended on initcall ordering to favor one zero-priority clocksource over another. With the move to deep probe and with Commit b641580deb8c ("of: platform: Ensure timers are probed early"), device tree blob iteration order could now dictate which clocksource is ultimately used. This led to a 20 times slower clock source being chosen on the Raspberry Pi, because the ARM architected timer was taken instead of the bcm2835 timer. Fix the root cause by assigning priorities to all clocksource drivers. Priorities chosen are: 50: device_initcall 60: coredevice_initcall 70: postcore_initcall 80: core_initcall These priorities are all below 100, which was previously the lowest positive priority and as they are positive, they win against the dummy clocksource. This should ensure no priority inversion happens. Fixes: b641580deb8c ("of: platform: Ensure timers are probed early") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220425094857.674044-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: fix optimised memset returning garbageDenis Orlov2022-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a subtle bug in arch/mips/lib/memset.S, used if option MIPS_OPTIMIZED_STRING_FUNCTIONS is enabled, which results in not writing the correct return value into v0 register if the value to fill memory with is 0. The bug stems from a missing '.set noreorder' directive before the first beqz instruction. This results in an assembler stuffing a 'nop' instruction in the beqz delay slot instead of an instruction writing the return value into v0 register that was supposed to go there. That leads to an error that appears when reading memory from SPI Flash and that was mentioned here: http://lists.infradead.org/pipermail/barebox/2021-June/036557.html There are a few ways of fixing this bug. The directive '.set noreorder' that shows up a bit later in code could be moved up and placed right before the memset label (as it was originally in Linux codebase - see a583158c9ce822c96a718fbf877cec1e5f9ad75d). Or, rather, the move and the branch instruction could be swapped, thus allowing the assembler to properly place move in delay slot (as it is done in Linux now - see 68dec269ee29c3abfd09596fbee7e40d875a6ab3) - that is what is done in this patch. Signed-off-by: Denis Orlov <denorl2009@gmail.com> Link: https://lore.barebox.org/20220310204206.31942-1-denorl2009@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arch: add SPDX-License-Identifier to all .c filesAhmad Fatoum2022-01-055-0/+10
| | | | | | | | | Record GPL-2.0-only as license for all files lacking an explicit license statement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arch: add SPDX-License-Identifier to all .S filesAhmad Fatoum2022-01-051-0/+2
| | | | | | | | | Record GPL-2.0-only as license for all files lacking an explicit license statement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-10-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: add SPDX-License-Identifier for .gitignoreAhmad Fatoum2022-01-051-0/+2
| | | | | | | | | Makes the files not appear when searching for files that lack SPDX-License-Identifier. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: add SPDX-License-Identifier for Kbuild/KconfigAhmad Fatoum2022-01-051-0/+2
| | | | | | | | | | | | | | | To verify only Kconfig/Makefile is touched: git show --numstat --format=oneline HEAD | grep -v 'Kconfig\|Makefile' will print only arch/powerpc/Kbuild. To verify nothing unexpected is added: git show -U0 | grep '^-[^-]\|^+[^+]' | sort -u Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220103120539.1730644-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* blspec: Rework firmware loadSascha Hauer2021-06-281-0/+4
| | | | | | | | | | | | | | | | Applying overlays in blspec currently works in two steps. First of_firmware_load_overlay() is called which doesn't load an overlay, but instead loads firmware when one is needed by the overlay. This is done on the live tree, because that was needed to find the firmware manager. The second step is to call of_register_overlay() to apply the overlay to the kernel device tree when the fixups are executed. Instead of using a separate step to load the firmware, load the firmware as part of the of_fixups. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210624085223.14616-14-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: Implement setjmp/longjmp/initjmp for 32BITSascha Hauer2021-03-172-0/+51
| | | | | | | | | The header has been taken from glibc, the implementation itself is based on the newlib implementation. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mips: lib: bootm: use bootm elf loading capabilitiesClement Leger2020-06-151-13/+7
| | | | | | | | | | Now that the elf file is loaded by the bootm core, there is no need for elf pointer anymore. Thus all elf related fields can be removed and bootm_load_os can be used. Signed-off-by: Clement Leger <cleger@kalray.eu> Tested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* common: elf: add elf_open, elf_close and elf_loadClement Leger2020-06-151-2/+6
| | | | | | | | | In order to integrate elf loading into bootm command, split elf opening from elf loading. Signed-off-by: Clement Leger <cleger@kalray.eu> Tested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* common: elf: load elf directly from fileClement Leger2020-06-151-7/+2
| | | | | | | | | | | | | | Currently, elf file must be loaded into a buffer and then passed to elf_load_image. This requires to copy the whole elf file before booting it. This commit allows to pass the filename directly and will allocate data only for the elf header (elf header + program headers). This will then be used to load the elf data from the file without copying it in an intermediate buffer. Elf segments are first parsed into a list and are then loaded from the file in a second time. Signed-off-by: Clement Leger <cleger@kalray.eu> Tested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: correctly work with disabled CONFIG_MMUAntony Pavlov2020-06-081-1/+5
| | | | | | | | | | | | | | There are some issues with CONFIG_MMU=n in MIPS configuration (e.g. qemu-malta_defconfig): * "Cannot request SDRAM region for stack" error message on start; * empty kseg1_ram0 region in the iomem command output. The patch fixes the problems by forcing KSEG1 memory region usage for CONFIG_MMU=n MIPS configurations. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: don't overlay relocation data with BSSOleksij Rempel2020-02-032-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .bss __rel_start (OVERLAY) was used to optimize RAM size used by barebox. Since .bss and __rel_start overlap, we should clear bss only after __rel_start was used. Following patch changed initialization sequence to clear .bss before __rel_start: 1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu") This make relocation buffer unusable and broke relocation with different symptoms reported by Antony Pavlov <antonynpavlov@gmail.com>: * iomem output has no information on sdram regions, so memtest is unusable; * pc = 0xa081232c, relocation does not work, barebox is located with 8M offset from start of RAM. The board has 256M and relocation routine should move barebox code much higher; * pc = 0xa081232c, so barebox code works from KSEG1 not from KSEG0 as MMU=y option implies. There is a choice of moving .bss clear sequence after __rel_start or remove this optimization. Since the use of this optimization is minimal and danger to trap in to similar issue is still high, i prefer to remove this optimization. As result of this change, we need to fix calculation of relocation are size: relocate_code() calculates relocation area size as a sum (barebox_image_size + bss_len). barebox_image_size and bss_len are calculated as (__image_end - __image_start) and (__bss_stop - __bss_start) respectively. This doesn't take into account relocation data placed between __image_end and __bss_start. However relocation preserves BSS position relative to image start, as if relocation data is still there. This causes RAM overflow during BSS initialization in main_entry(). This problem may be hidden due to the alignment of the `relocaddr`. Reported-by: Antony Pavlov <antonynpavlov@gmail.com> Fixes: 1e5aef61fc6a444 ("MIPS: reloc: init bss and cpu") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: actually use CONFIG_MIPS_RELOCATION_TABLE_SIZEAntony Pavlov2020-01-161-1/+1
| | | | | | | | | The commit 28ed10d6a67c9 ("MIPS: relocation: add relocation support") introduce the Kconfig CONFIG_MIPS_RELOCATION_TABLE_SIZE parameter but it is never used. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: loongson: rename CPU_LOONGSON1 to CPU_GS232Du Huanpeng2020-01-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU in the loongson 1b SoC is called GS232. Here is some active chips and it's core: NAME CPU Core(s) The loongson 3 series/server & desktop 3A3000/3B3000 GS464E 64bit x4 3A2000/3B2000 GS464E 64bit x4 3B1500 GS464 64bit x8 3A1000 GS464 64bit x4 The loongson 2 series/low power 2K1000 GS264 64bit x2 2F GS464 64bit x1 2H GS464 64bit x1 The loongson 1 series/embeded 1C101 GS132R 32bit ? 1D GS132 32bit ? 1C GS232 32bit x1 1B GS232 32bit x1 1A GS232 32bit x1 see: [1] http://www.loongson.cn/product/ Signed-off-by: Du Huanpeng <duhuanpeng@loongson.cn> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: reloc: init bss and cpuOleksij Rempel2019-10-231-0/+2
| | | | | | | We need it to make flush_cache_all() work properly. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: move r4k_cache_init in to cpu_probe functionOleksij Rempel2019-10-231-0/+5
| | | | | Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: reloc: remove init of relocated bssOleksij Rempel2019-10-231-5/+1
| | | | | | | It will be done in main_entry() any way. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: Add and use RO_DATA_SECTION macroSascha Hauer2019-10-141-12/+4
| | | | | | | | | We have many different pointer arrays which we put into linker sections and each time there's one added we have to adjust all linker scripts. This adds a common RO_DATA_SECTION define and uses it for all architectures. This makes it easier to add a new linker array. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: create and use BAREBOX_PCI_FIXUP macroSascha Hauer2019-10-141-13/+1
| | | | | | | No need to repeat the pci fixup sections in each linker script. Add a define for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* lds: Move start/end address variables into definesSascha Hauer2019-10-141-19/+2
| | | | | | | | | | | For the older section defines we specify the start and end addresses outside the macro which means we have to repeat them in each linker script. Make the start/end addresses part of the define to simplify things. While at it, add a BAREBOX_ prefix to the INITCALLS and EXITCALLS macros for consistency to the other defines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Sam Ravnborg <sam@ravnborg.org>
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