summaryrefslogtreecommitdiffstats
path: root/arch/openrisc/configs/generic_defconfig
Commit message (Collapse)AuthorAgeFilesLines
* openrisc: generic_defconfig: enable device tree stuffAntony Pavlov2014-09-091-13/+22
| | | | | | | | Also enable iomem and miitool. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Cc: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* commands: NET_DHCP -> CMD_DHCPHolger Schurig2014-05-141-1/+1
| | | | | | | | | | | * this compile option actually turns on a command, so name it accordingly * also move the Kconfig definition into commands/Kconfig, thus placing getopt into the "Network commands" section * while at it, improve Kconfig documention Signed-off-by: Holger Schurig <holgerschurig@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* commands: NET_PING -> CMD_PINGHolger Schurig2014-05-141-1/+1
| | | | | | | | | | | * this compile option actually turns on a command, so name it accordingly * also move the Kconfig definition into commands/Kconfig, thus placing getopt into the "Network commands" section * while at it, improve Kconfig documention Signed-off-by: Holger Schurig <holgerschurig@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* openrisc: enable OpenCores ethernet driverBeniamino Galvani2013-12-171-0/+6
| | | | | | | | | | | The OpenCores 10/100 Mbps ethernet MAC is often available on OpenRISC-based SoCs and is supported by the OpenRISC architectural simulator (or1ksim) as well. The patch enables the driver on the 'generic' openrisc board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* openrisc: switch to defaultenv-2 and change boardinfoFranck Jullien2012-10-211-2/+2
| | | | | Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add OpenRISC archFranck Jullien2012-01-021-0/+20
OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. Even though I should have created an mach-or1200 directory, it is not necessary for now. The OpenRISC 1200 CPU is the only one available and it will be for some time. Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>