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* rework remap_rangeSascha Hauer2015-11-031-11/+15
| | | | | | | | | | | | | | | | | | remap_range is for remapping regions with different cache attributes. It is implemented for ARM and PowerPC only, the other architectures only provide stubs. Currently the new cache attributes are passed in an architecture specific way and the attributes have to be retrieved by calls to mmu_get_pte_cached_flags() and mmu_get_pte_uncached_flags(). Make this simpler by providing architecture independent flags which can be directly passed to remap_range() Also provide a MAP_ARCH_DEFAULT flag and a arch_can_remap() function. The MAP_ARCH_DEFAULT defaults to whatever caching type the architecture has as default. the arch_can_remap() function returns true if the architecture can change the cache attributes, false otherwise. This allows the memtest code to better find out what it has to do. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ppc: 85xx: CCSRBAR mapping moved to start-up code.Renaud Barbier2014-07-281-0/+106
| | | | | | | | | | Move the configuration, control and status register base address (CCSRBAR) relocation to the start-up processing. This addresses TLB faults found during testing on the Freescale P1010RDB and also matches the current U-Boot functionality. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ppc: add Freescale P1022DS board supportRenaud Barbier2014-03-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Add support for the Freescale P1022DS. Driver support is limited to: - I2C - Ethernet - Serial - NOR flash - PIXIS FPGA System clock configuration is read from the FPGA but has only been tested using a 133MHz system clock and 100MHz DDR clock. Boot arguments are defined in the environment to boot over NFS with a console configured at 115200 bauds. Enabling branch prediction is moved from board support to the platform support for all boards as it is a CPU feature. Some the code is from U-Boot version git-be937b5. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ppc: add support for memtest with cache disabledRenaud Barbier2014-03-033-1/+71
| | | | | | | | | Add support to enable caching on a memory region during the memory test. Tested on P2020RDB and DA923RC. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MPC85xx: fix memory layout to prevent corruption during memtestRenaud Barbier2014-03-031-3/+0
| | | | | | | | | | | | Memory regions on MPC85xx boards are incorrectly defined leading to corruption when running memory tests. This patch updates the memory layout of MPC85xx boards so that critical memory regions can be correctly reserved during the memory test. Tested on the P2020RDB and DA923RC. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/ppc'Sascha Hauer2014-02-032-161/+300
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| * cpu-85xx: start.S: clean up imported codeRenaud Barbier2014-01-161-11/+11
| | | | | | | | | | | | | | | | Correct double spaces, indentation and vocabulary in the imported start-up code. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ppc: cpu-85xx: import U-Boot start-up codeRenaud Barbier2014-01-161-128/+267
| | | | | | | | | | | | | | | | | | Import U-Boot start-up code from version git-9407c3fc to include the latest CPUs errata and make future U-Boot code inclusion easier. The code import is limited to the currently supported CPUs P2020/MPC8544. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ppc: mpc85xx: change bss relocationRenaud Barbier2014-01-161-22/+14
| | | | | | | | | | | | | | | | | | The linker script and start up code are updated so that the bss section is located above the barebox binary in memory. This removes the reliance on a hard-coded value. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ppc: cpu-85xx: upgrade MMU support to v2 pages sizesRenaud Barbier2014-01-161-11/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | TLB support for the 85xx CPUs has been upgraded to support the MMUv2 page size definitions. This has been imported from U-Boot version git-9407c3fc. This allows for future CPUs to make use of the new MMU support. Also the definition of MAX_MEM_MAPPED has been changed to avoid type casting with "min" macro. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ppc: remove bit operation headers file conflictRenaud Barbier2014-01-301-1/+1
|/ | | | | | | | | | | | | Removed the ppc bit operation functions and definitions in the ppc file asm/bitops.h since these are already defined in the asm-generic header files. Moved ffs64 definition to the mpc85xx header files because the function requires the inclusion of linux/log2.h which also includes asm/bitops.h. The conflict was noted when UBIFS was enabled in barebox. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mpc85xx: remove local bus initialisationRenaud Barbier2013-08-051-1/+0
| | | | | | | | | | | | | The early initialisation of chip select 0 (boot flash) is removed from cpu initialisation. This removes the dependency on board base address definition. Consequently, cpu_init_f is not called in the start-up code but added to the init call list as cpu_init_r. Also the file arch/ppc/mach-mpc85xx/fsl_lbc.c is deleted. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Treewide: remove address of the Free Software FoundationSascha Hauer2012-09-174-16/+0
| | | | | | | The FSF address has changed in the past. Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ppc 85xx: Fix whitespacesSascha Hauer2012-05-241-3/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* e500v2 traps and TLB support codeRenaud Barbier2012-05-174-0/+512
| | | | | | | | | | This patch defines functions to set interrupt vector registers and functions to handle hardware exceptions. It also defines support functions to set and search TLBs. Finally, the Makefile is added. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Initial e500v2 start up codeRenaud Barbier2012-05-172-0/+1087
This is the first part of the start-up code. The source code origin is U-boot and is slightly modified to have e500v2 CPU support in 32-bit mode only. It includes the power-up entry point, CPU initialization code and exports definition for D-cache flush and I-cache invalidate. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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