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* kvx,openrisc,riscv,sandbox/dts: harmonize clean-files definitionUwe Kleine-König2022-12-021-1/+1
| | | | | | | | | | | | I noticed while playing around with the sandbox that the mrproper make target doesn't remove arch/sandbox/dts/sandbox.dtb.z. Fix all dts clean-files defintion to match arm's defintion which seems to be the most complete one. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.barebox.org/20221202082954.3413605-1-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add LiteX SoC and linux-on-litex-vexriscv supportAntony Pavlov2021-10-071-0/+1
| | | | | | | | | | | | | | LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210817101104.114945-8-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: StarFive: add board support for BeagleV StarlightAhmad Fatoum2021-06-241-0/+1
| | | | | | | | | With the different drivers now in place, we have everything to start a barebox image. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-30-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: sifive: add HiFive board supportAhmad Fatoum2021-05-171-0/+2
| | | | | | | | | | | | | | | | | With the recently added SiFive support, we now have enough functionality to boot a HiFive board to shell: qemu-system-riscv64 -M sifive_u serial_stdio \ -kernel./images/barebox-hifive-unleashed.img Some more drivers need to be ported for this to be useful: - sifive,spi0 needed for talking to SD-Card - clocksource The riscv-timer seems to be 10x too fast Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210427202309.32077-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo: migrate to PBLAhmad Fatoum2021-03-231-6/+3
| | | | | | | | | | We now have everything in place to migrate erizo to PBL. As currently, this is the only board, we can drop all non-PBL support in the same go. Cc: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kvx,riscv: remove unused $(dtb-y) assignmentMasahiro Yamada2020-08-191-1/+0
| | | | | | | dtb-y is not defined in these Makefiles. Remove the meaningless code. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kbuild: remove obj-dtb-y, pbl-dtb-y, lwl-dtb-y syntaxMasahiro Yamada2020-05-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The embedded DTBs are compiled by the chain of pattern rules as follows: %.dts -> %.dtb -> %.dtb.S -> %.dtb.o for barebox proper %.dts -> %.dtb -> %.dtb.S -> %.dtb.pbl.o for pbl Barebox introduced {obj,pbl,lwl}-dtb-y syntax to put the intermediate files into extra-y. The purposes of doing so were: [1] prevent GNU Make from deleting the intermediate files [2] include .*.cmd files In contrast, Linux does not use a special syntax for embedding DTBs into the kernel. For example, as you see in arch/sh/boot/dts/Makefile of Linux 5.6, obj-y += <basename>.dtb.o ... just works. This is because scripts/Kbuild.include specifies .SECONDARY to cater to [1], and scripts/Makefile.build adds the intermediates to 'targets' to deal with [2]. Barebox had already imported the same code from Linux, so you can use obj-y instead of obj-dtb-y, like Linux. pbl-dtb-y and lwl-dtb-y are barebox-specific cases, so I added the %.dtb.pbl.o pattern to intermediate_targets. Going forward, please use obj-y, pbl-y, or lwl-y. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add Erizo SoC supportAntony Pavlov2019-01-071-0/+2
| | | | | | | Erizo is an opensource hardware SoC for FPGA. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add initial RISC-V architecture supportAntony Pavlov2019-01-071-0/+11
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>