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* RISC-V: StarFive: J7100: set /soc/dma-noncoherentAhmad Fatoum2024-01-111-0/+1
| | | | | | | | | | With upcoming changes, cache handling will be skipped on RISC-V, because arch is cache-coherent by default. StarFive JH7100 has non-coherent DMA masters though, so note that in the DT. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240110160112.4134162-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: sifive: disable non-functional SPI nodesAhmad Fatoum2023-04-112-0/+9
| | | | | | | | | | | | For some reasons,newer QEMU versions (tested v5.2.0) trigger a load fault at the first readl of the driver. For now disable the nodes, until this issue is looked into. Reported-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/barebox/20220830140533.deb229d3e3f32c827e6ff521@gmail.com/ Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230411071436.1630752-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kvx,openrisc,riscv,sandbox/dts: harmonize clean-files definitionUwe Kleine-König2022-12-021-1/+1
| | | | | | | | | | | | I noticed while playing around with the sandbox that the mrproper make target doesn't remove arch/sandbox/dts/sandbox.dtb.z. Fix all dts clean-files defintion to match arm's defintion which seems to be the most complete one. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.barebox.org/20221202082954.3413605-1-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* gitignore: add device tree blobs to top-level .gitignoreAhmad Fatoum2022-08-081-1/+0
| | | | | | | | | We have device trees outside of the usual directories, e.g. for overlays, so move the .gitignore rule to top-level. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20220805085314.3404920-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add LiteX SoC and linux-on-litex-vexriscv supportAntony Pavlov2021-10-073-0/+142
| | | | | | | | | | | | | | LiteX is a Migen-based System on Chip, supporting softcore VexRiscv CPU, a 32-bits Linux Capable RISC-V CPU. See https://github.com/enjoy-digital/litex and https://github.com/litex-hub/linux-on-litex-vexriscv for details. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210817101104.114945-8-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clocksource: timer-riscv: select CSR from device treeAntony Pavlov2021-10-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | barebox timer-riscv driver supports one of user counters: * 'cycle', counter for RDCYCLE instruction (CSR 0xc00); * 'time', timer for RDTIME instruction (CSR 0xc01). At the moment in M-mode timer-riscv uses the 'cycle' counter, and in S-mode timer-riscv uses the 'time' timer. Alas picorv32 CPU core supports only the 'cycle' counter. VexRiscV CPU core in M-mode supports only the 'time' timer. This patch makes it possible to use the 'time' timer for VexRiscV CPU in M-mode. See also http://lists.infradead.org/pipermail/barebox/2021-May/036067.html Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210817101104.114945-2-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: StarFive: add board support for BeagleV StarlightAhmad Fatoum2021-06-244-0/+1222
| | | | | | | | | With the different drivers now in place, we have everything to start a barebox image. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210619045055.779-30-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: sifive: add HiFive board supportAhmad Fatoum2021-05-173-0/+8
| | | | | | | | | | | | | | | | | With the recently added SiFive support, we now have enough functionality to boot a HiFive board to shell: qemu-system-riscv64 -M sifive_u serial_stdio \ -kernel./images/barebox-hifive-unleashed.img Some more drivers need to be ported for this to be useful: - sifive,spi0 needed for talking to SD-Card - clocksource The riscv-timer seems to be 10x too fast Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210427202309.32077-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo.dtsi: set timebase-frequency = <24000000>Antony Pavlov2021-03-301-0/+2
| | | | | | | | | | | This patch makes it possible to use drivers/clocksource/timer-riscv.c with erizo. Without timebase-frequency initialized we have this warning at startup: RISC-V system with no 'timebase-frequency' in DTS Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clocksource: add driver for RISC-V and CLINT timersAhmad Fatoum2021-03-231-1/+1
| | | | | | | | | | | | | CLINT is selected by Linux on nommu RISC-V machines, while the RISC-V timer with SBI is selected on MMU enabled ones. Both are also available on the Qemu Virt machine, but only SBI is available on TinyEmu. As we'll add Virt support in a follow-up commit, import both drivers now. Erizo could in theory make use of the RISC-V timer, but even a 2GHz timer base is too slow for it to be accurate. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: erizo: migrate to PBLAhmad Fatoum2021-03-231-6/+3
| | | | | | | | | | We now have everything in place to migrate erizo to PBL. As currently, this is the only board, we can drop all non-PBL support in the same go. Cc: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kvx,riscv: remove unused $(dtb-y) assignmentMasahiro Yamada2020-08-191-1/+0
| | | | | | | dtb-y is not defined in these Makefiles. Remove the meaningless code. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* kbuild: remove obj-dtb-y, pbl-dtb-y, lwl-dtb-y syntaxMasahiro Yamada2020-05-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The embedded DTBs are compiled by the chain of pattern rules as follows: %.dts -> %.dtb -> %.dtb.S -> %.dtb.o for barebox proper %.dts -> %.dtb -> %.dtb.S -> %.dtb.pbl.o for pbl Barebox introduced {obj,pbl,lwl}-dtb-y syntax to put the intermediate files into extra-y. The purposes of doing so were: [1] prevent GNU Make from deleting the intermediate files [2] include .*.cmd files In contrast, Linux does not use a special syntax for embedding DTBs into the kernel. For example, as you see in arch/sh/boot/dts/Makefile of Linux 5.6, obj-y += <basename>.dtb.o ... just works. This is because scripts/Kbuild.include specifies .SECONDARY to cater to [1], and scripts/Makefile.build adds the intermediates to 'targets' to deal with [2]. Barebox had already imported the same code from Linux, so you can use obj-y instead of obj-dtb-y, like Linux. pbl-dtb-y and lwl-dtb-y are barebox-specific cases, so I added the %.dtb.pbl.o pattern to intermediate_targets. Going forward, please use obj-y, pbl-y, or lwl-y. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* riscv: dts: erizo-generic: fix memory node nameAntony Pavlov2019-06-041-1/+1
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: add Erizo SoC supportAntony Pavlov2019-01-073-0/+62
| | | | | | | Erizo is an opensource hardware SoC for FPGA. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Add initial RISC-V architecture supportAntony Pavlov2019-01-072-0/+12
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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