| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
| |
commit d7a913469c34553e96c887f8a9934bacd794e81c breaks boot source detection
for pcm049. The tracing vectors shows all tested boot sources, so order is
important. By not returning but overwriting src we effectively reversed the
order if more than one flag is set.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
| |
In case he configures with make ARCH=x85 menuconfig,
config SPI will be set to "y". And he will got an error on spi.h.
Signed-off-by: Masaki Muranaka <monaka@monami-ya.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
| |
We always must decend into the pbl build. Otherwise it doesn't get
rebuilt if only sourcefiles from the pbl are changed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
| |
This is a i.MX53 board, not i.MX51.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
| |
The default baseboard for the tqma53 (MBa53) uses UART2 for debug console.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
| |
Add a command to generate the zynq image instead of generating it
directly. This causes a rebuild exactly when necessary and prints
a "ZYNQ-IMG" to the commandline during compilation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
| |
The pbl used 'zbarebox.bin' as target instead of the real file. This
lead to strange effects that the images depending on zbarebox.bin were
only built every second time. This uses the full path as target.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
| |
Some SoCs come up with invalid entries in the data cache. This can
lead to memory corruption when we enable them later, so invalidate
the caches early.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Lucas Stach <l.stach@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
At least the iMX6 boot rom seems to jump into barebox with a non
invalidated d-cache which causes data corruption when
v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides
stack or other valid data.
That's why the cache must be invalided for this processors explicitly
(e.g. in barebox_arm_reset_vector()). Operation differs from flush only
in one instruction so that patch modifies the existing
v7_mmu_cache_flush() function slightly by adding an optional argument.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
| |
Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
| |
On ARMv7 the intention is to disable the alignment trap to be able to
use hardware assisted unaligned load/stores. Fix the init to do the
right thing.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
From Kernel commit 418df63a ARM: 7670/1: fix the memset fix
| Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
| recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
| with the memset return value. However the memset itself became broken
| by that patch for misaligned pointers.
|
| This fixes the above by branching over the entry code from the
| misaligned fixup code to avoid reloading the original pointer.
|
| Also, because the function entry alignment is wrong in the Thumb mode
| compilation, that fixup code is moved to the end.
|
| While at it, the entry instructions are slightly reworked to help dual
| issue pipelines.
|
| Signed-off-by: Nicolas Pitre <nico@linaro.org>
| Tested-by: Alexander Holler <holler@ahsoftware.de>
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Although conclusions in 50d1b2de8ea0f3b8d89fe3a97ce64315996ed4cb "ARM
v7: Fix register corruption in v7_mmu_cache_off" are correct, the
implemented fix is not complete because the following failure can
happen:
1. d-cache contains the cache line around 'sp'
2. v7_mmu_cache_off() disables cache
3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack
4. v7_mmu_cache_flush() flushes d-cache and can override stack written
by step 3.
5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which
might be random data now.
Patch avoids step 3 which is easy because 'lr' is never modified by the
function. By using the 'r12' scratch register instead of 'r10', the
whole initial 'push' can be avoided.
Patch moves also the 'DMB' operation so that it is executed after data
has been pushed on stack.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
| |
For CCMX51-boards now we do not use ESDCTL, but actual command for
adding memory is missing. This patch fix this issue.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
See also:
commit eb84709192f1b616cd141594c34ddbc072c8d6ec
Author: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon Mar 25 15:18:38 2013 +0100
clk: remove unused __clk_[get|put]
This is some unused code resulting from copying stuff from
the kernel. Remove it.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
| |
The missing 'break' statement lets look an i.MX23 like an i.MX28.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This partly reverts:
commit 697e02b74fddd80527e8ababba10239c83dba029
Author: Alexander Shiyan <shc_work@mail.ru>
Date: Tue Jan 22 15:08:31 2013 +0400
ARM: ccmx51: Remove SDRAM size settings
This patch removes SDRAM memory size setting from board due
to auto detect last one by ESDCTL.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.
This patch brings back the old behaviour.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
| |
Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
| |
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In commit ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 "ARM i.MX31: give
register base addresses a proper MX31_ prefix", the IOMUX GPR setup
to enable USBH2 was replaced with an incorrect source register.
Instead of reading the GPR register, USBOTG HWHOST is used as rmw source,
which contains 0x10020001.
Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and
AudioPort6"), this erroneously also sets
GPR[28] enable USBOTG loopback
GPR[17] override DSR_DCE1 with USBOTG_DATA4
GPR[0] select FIR DMA requests instead of UART2 DMA
Beside breaking UART2, it probably also broke some UART1 and USB OTG setups.
Fix this and replace the address with the appropriate defines.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
|
|
|
|
|
|
|
|
|
| |
The prefix/cleanup series
ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1
a8c6359667704ffc3bd2249dd76f3fbbb2134b55
4c53af062b38f15f6bc40c586e5760e640f5b8b1
missed a few unprefixed IOMUXC_BASE define users. Fix these.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| |
| | |
Taken from the Linux kernel, simplified and reworked to match barebox.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
ODMdata tells us how much RAM is installed, so no need to define this at
the board level.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
ODMdata tells us which UART to use for debugging purposes. This is
agreed upon in both the upstream Linux kernel and U-Boot, so do it the
same way in barebox.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
All Tegra20 boards have a common startup sequence. Also there is an
agreement on how to find out about the installed amount of RAM and other
information needed by early startup. So as there is really no need to do
any lowlevel stuff per board, we can just do it at the ARCH level.
This also enables the first stage loading of barebox by detecting the
currently running CPU and booting the main CPU cluster if neccesary.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Currently only implements system wide reset functionality.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Replace the ad-hoc clocksource implementation with a proper driver for
the Tegra 20 timer. This driver is able to do the required hardware
initialisation itself.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Only a basic set of clocks is supported. This is a temporary solution
and will go away as soon as the port of the Tegra common clock code from
the Linux kernel is ready to go.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
We will follow the Linux kernel and go devicetree only for Tegra. This
doesn't prevent specific code for certain boards, but always requires a
valid DTB for all boards.
Also regenerate the AC100 defconfig to reflect this change.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
All available opensource tools and published BCT configurations use
0x10800 as the default textbase on Tegra 20.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Tegra isn't a single architecture, but a collection of more or less
similar chip families. Introduce the same conf define as used in the
Linux kernel to differentiate between those families.
Currently we are only supporting the Tegra20 chip type.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| | |
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| | |
Tegras main CPUs are all ARMv7.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ |
|
| |/
| |
| |
| |
| | |
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \
| | |
| | |
| | |
| | | |
Conflicts:
drivers/mci/mci-core.c
|
| | |
| | |
| | |
| | | |
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | | |
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |/
| |
| |
| | |
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This patch includes no functional change. If a configurable DDRPLL_M
is required later, it should be set by the board instead of from here.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The *PLL_N values can be calculated from the OSC value. This patch
includes no functional change.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | | |
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | | |
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Folded fix into this patch:
[PATCH] omap4 regression: set correct boot source
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
|
| |/
| |
| |
| |
| |
| |
| |
| |
| | |
On OMAP4 SoC there is a SAR memory region (Save & Rescue)
where the ROM code reads the device to boot from.
This patch adds a way to set this.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \
| | |
| | |
| | |
| | | |
Conflicts:
arch/arm/mach-imx/Makefile
|
| | |
| | |
| | |
| | |
| | |
| | | |
For consistency reasons.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | | |
For consistency reasons.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|