summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* ARM v7: fix mmu-off operationEnrico Scholz2013-05-171-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although conclusions in 50d1b2de8ea0f3b8d89fe3a97ce64315996ed4cb "ARM v7: Fix register corruption in v7_mmu_cache_off" are correct, the implemented fix is not complete because the following failure can happen: 1. d-cache contains the cache line around 'sp' 2. v7_mmu_cache_off() disables cache 3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack 4. v7_mmu_cache_flush() flushes d-cache and can override stack written by step 3. 5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which might be random data now. Patch avoids step 3 which is easy because 'lr' is never modified by the function. By using the 'r12' scratch register instead of 'r10', the whole initial 'push' can be avoided. Patch moves also the 'DMB' operation so that it is executed after data has been pushed on stack. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: ccmx51: Another fix SDRAM size detectionAlexander Shiyan2013-05-151-2/+10
| | | | | | | | For CCMX51-boards now we do not use ESDCTL, but actual command for adding memory is missing. This patch fix this issue. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: remove unused clkdev.hAntony Pavlov2013-05-122-13/+0
| | | | | | | | | | | | | | | | See also: commit eb84709192f1b616cd141594c34ddbc072c8d6ec Author: Sascha Hauer <s.hauer@pengutronix.de> Date: Mon Mar 25 15:18:38 2013 +0100 clk: remove unused __clk_[get|put] This is some unused code resulting from copying stuff from the kernel. Remove it. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXS: fix SoC detectingJuergen Beisert2013-05-081-0/+1
| | | | | | | The missing 'break' statement lets look an i.MX23 like an i.MX28. Signed-off-by: Juergen Beisert <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: ccxmx51: detect SDRAM size by board idSascha Hauer2013-05-083-21/+39
| | | | | | | | | | | | | | | | | | | | | | | | | This partly reverts: commit 697e02b74fddd80527e8ababba10239c83dba029 Author: Alexander Shiyan <shc_work@mail.ru> Date: Tue Jan 22 15:08:31 2013 +0400 ARM: ccmx51: Remove SDRAM size settings This patch removes SDRAM memory size setting from board due to auto detect last one by ESDCTL. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> The board originally configured the SDRAM controller for the maximum size and detected the usable SDRAM size by reading the board id. This became broken after switching to automatic SDRAM size detection by reading back ESDCTL values. This patch brings back the old behaviour. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: Allow disabling SDRAM autodetectionSascha Hauer2013-05-082-0/+15
| | | | | | | Some boards setup more memory than they actually have. The real memory size can then be detected later for example by reading a board id. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sama5d3xek: correct rootfs nand partitionAlexandre Belloni2013-05-081-1/+1
| | | | | Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX31 pcm037: fix erroneous IOMUX GPR setup in pcm037_usb_init()Andreas Pretzsch2013-05-071-3/+3
| | | | | | | | | | | | | | | | | | | In commit ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 "ARM i.MX31: give register base addresses a proper MX31_ prefix", the IOMUX GPR setup to enable USBH2 was replaced with an incorrect source register. Instead of reading the GPR register, USBOTG HWHOST is used as rmw source, which contains 0x10020001. Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and AudioPort6"), this erroneously also sets GPR[28] enable USBOTG loopback GPR[17] override DSR_DCE1 with USBOTG_DATA4 GPR[0] select FIR DMA requests instead of UART2 DMA Beside breaking UART2, it probably also broke some UART1 and USB OTG setups. Fix this and replace the address with the appropriate defines. Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX31: cleanup MX31_ prefix: fix leftover IOMUXC_BASE definesAndreas Pretzsch2013-05-071-3/+3
| | | | | | | | | | | The prefix/cleanup series ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 a8c6359667704ffc3bd2249dd76f3fbbb2134b55 4c53af062b38f15f6bc40c586e5760e640f5b8b1 missed a few unprefixed IOMUXC_BASE define users. Fix these. Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/tegra'Sascha Hauer2013-05-0624-162/+1172
|\
| * tegra: add GPIO controller driverLucas Stach2013-04-143-0/+19
| | | | | | | | | | | | | | | | Taken from the Linux kernel, simplified and reworked to match barebox. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add generic meminitLucas Stach2013-04-142-8/+9
| | | | | | | | | | | | | | | | | | ODMdata tells us how much RAM is installed, so no need to define this at the board level. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add generic debug UART supportLucas Stach2013-04-147-40/+125
| | | | | | | | | | | | | | | | | | | | ODMdata tells us which UART to use for debugging purposes. This is agreed upon in both the upstream Linux kernel and U-Boot, so do it the same way in barebox. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add common lowlevel startupLucas Stach2013-04-149-11/+577
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All Tegra20 boards have a common startup sequence. Also there is an agreement on how to find out about the installed amount of RAM and other information needed by early startup. So as there is really no need to do any lowlevel stuff per board, we can just do it at the ARCH level. This also enables the first stage loading of barebox by detecting the currently running CPU and booting the main CPU cluster if neccesary. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add T20 power management controller driverLucas Stach2013-04-145-40/+111
| | | | | | | | | | | | | | | | Currently only implements system wide reset functionality. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add T20 timer driverLucas Stach2013-04-145-57/+133
| | | | | | | | | | | | | | | | | | | | Replace the ad-hoc clocksource implementation with a proper driver for the Tegra 20 timer. This driver is able to do the required hardware initialisation itself. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: add driver for the clock and reset moduleLucas Stach2013-04-146-0/+154
| | | | | | | | | | | | | | | | | | | | Only a basic set of clocks is supported. This is a temporary solution and will go away as soon as the port of the Tegra common clock code from the Linux kernel is ready to go. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: switch to DT onlyLucas Stach2013-04-144-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | We will follow the Linux kernel and go devicetree only for Tegra. This doesn't prevent specific code for certain boards, but always requires a valid DTB for all boards. Also regenerate the AC100 defconfig to reflect this change. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: move default textbaseLucas Stach2013-04-141-1/+1
| | | | | | | | | | | | | | | | | | All available opensource tools and published BCT configurations use 0x10800 as the default textbase on Tegra 20. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: introduce Tegra 20 SoC typeLucas Stach2013-04-141-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | Tegra isn't a single architecture, but a collection of more or less similar chip families. Introduce the same conf define as used in the Linux kernel to differentiate between those families. Currently we are only supporting the Tegra20 chip type. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: unify spelling in Kconfig with Linux kernelLucas Stach2013-04-141-1/+1
| | | | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * tegra: switch to proper CPU typeLucas Stach2013-04-141-1/+1
| | | | | | | | | | | | | | | | Tegras main CPUs are all ARMv7. Signed-off-by: Lucas Stach <dev@lynxeye.de> Tested-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/remove-config-h'Sascha Hauer2013-05-0652-676/+0
|\ \
| * | Remove unused config.hAlexander Shiyan2013-04-0952-676/+0
| |/ | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/param'Sascha Hauer2013-05-065-93/+24
|\ \ | | | | | | | | | | | | Conflicts: drivers/mci/mci-core.c
| * | ARM: MXS: ocotp: Use dev_add_param_bool for parameterSascha Hauer2013-04-111-30/+4
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: iim: Use dev_add_param_bool for parametersSascha Hauer2013-04-111-51/+14
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | treewide: Use dev_add_param_int_ro where possibleSascha Hauer2013-04-113-12/+6
| |/ | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/omap'Sascha Hauer2013-05-0613-68/+193
|\ \
| * | m33xx-clock: remove unused codeJan Luebbe2013-04-191-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch includes no functional change. If a configurable DDRPLL_M is required later, it should be set by the board instead of from here. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | m33xx-clock: configure PLLs based on oscillator frequencyJan Luebbe2013-04-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The *PLL_N values can be calculated from the OSC value. This patch includes no functional change. Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | am33xx: add defines for GPIOsJan Luebbe2013-04-192-0/+8
| | | | | | | | | | | | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | beaglebone: remove stray semicolonJan Luebbe2013-04-181-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | omap: move to common bootsource frameworkJan Luebbe2013-04-186-56/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Folded fix into this patch: [PATCH] omap4 regression: set correct boot source Signed-off-by: Vicente Bergas <vicencb@gmail.com>
| * | OMAP4: add command to select next boot device priorityVicente Bergas2013-04-115-0/+131
| |/ | | | | | | | | | | | | | | | | On OMAP4 SoC there is a SAR memory region (Save & Rescue) where the ROM code reads the device to boot from. This patch adds a way to set this. Signed-off-by: Vicente Bergas <vicencb@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/of'Sascha Hauer2013-05-065-384/+18
|\ \ | | | | | | | | | | | | Conflicts: arch/arm/mach-imx/Makefile
| * | pinctrl: move imx-iomux-v1 to drivers/pinctrl/Sascha Hauer2013-04-233-119/+6
| | | | | | | | | | | | | | | | | | For consistency reasons. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | pinctrl: move imx-iomux-v2 to drivers/pinctrl/Sascha Hauer2013-04-233-153/+2
| | | | | | | | | | | | | | | | | | For consistency reasons. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | pinctrl: switch i.MX iomux-v3 support to pinctrlSascha Hauer2013-04-233-112/+10
| |/ | | | | | | | | | | | | | | | | This switches the iomux-v3 (found on i.MX25,35,51,53,6) to pinctrl support. The old SoC specific API is kept for compatibility. The pinctrl devicetree support is enabled automatically when OFDEVICE support is available. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2013-05-0627-70/+192
|\ \
| * | ARM: at91 smc: Fix possible uninitialized variableAlexander Shiyan2013-04-301-4/+4
| | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: at91 gpio: Fix possible null pointer dereferenceAlexander Shiyan2013-04-301-2/+3
| | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: imx: Fix incorrect Kconfig symbols for some boardsAlexander Shiyan2013-04-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This patch fix incorrect Kconfig symbols for MACH_FREESCALE_MX51_PDK, MACH_FREESCALE_MX53_LOCO and MACH_FREESCALE_MX53_SMD. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: netx: Remove references for missing boardsAlexander Shiyan2013-04-301-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | Barebox do not have support for MACH_NXDKN, MACH_NXHMIBB, MACH_NXEB500HMI and MACH_NXHX boards, so remove these symbols. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: omap: Remove wrong OMAP_CLOCK_ALL symbolAlexander Shiyan2013-04-303-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | OMAP_CLOCK_ALL is missing in Kconfig, so remove the "select" statement and all other references to this symbol. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: mmu: Use PAGE_ALIGN in dma_free_coherentJan Weitzel2013-04-271-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | We PAGE_ALIGN the size in dma_alloc_coherent so do it also when free the memory. Use PAGE_SIZE instead of magic numbers. Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | highbank: switch to defaultenv-2Jean-Christophe PLAGNIOL-VILLARD2013-04-0919-33/+178
| |/ | | | | | | | | | | | | | | this will allow to have boot sequence and later to use PXE Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2013-05-066-29/+60
|\ \
| * | ARM: ccmx51js: Add support for USB Host1Alexander Shiyan2013-05-061-0/+15
| | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: pcm038: Add definition for FEC resetAlexander Shiyan2013-05-041-0/+3
| | | | | | | | | | | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 17:42:58 +0000