| Commit message (Collapse) | Author | Age | Files | Lines |
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The optimized find bit functions are only implemented for 32 bit and are
not built on aarch64 systems. Therefore, for example bootchooser cannot
be build for aarch64.
Select the generic find_bit implementations on aarch64.
As the decision, if lib64 or lib32 is build or not, directly depends on
CPU_V8, the generic implementation also should be used if CPU_V8 is
selected.
Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The RDU3 shares some of the board fixups with the other Zii boards.
For those to work ZII_COMMON needs to be enabled.
Fixes: d76ba38a1605 (ARM: zii-common: reuse i210 config check for RDU3)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't
execute IPU QoS setup on MX6 SX/SL"), but instead it bails at
the Solo, not the SX and SL.
The original intent was most probably to add an exception for
the i.MX6 Solo as well, so everything else is skipped, including
the SX, SL and now the UL and ULL. Fix the code to reflect this.
On the SX, SL, UL, ULL, this now avoids writes to memory, which
isn't described in the datasheets. On the S, it now configures
the QoS settings.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In the device tree, the clock controller is a subnode of the firmware
node. Devices refer to the clocks by an id that is shared between the
ATF and the driver.
While the bindings for the clock controller are already upstream, the
device in mainline Linux does not use them, yet. Add them in the Barebox
device tree for now.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add firmware DT node in ZynqMP device tree. This node uses bindings as
per new firmware interface driver.
Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In order to use the query() call, the users of the firmware driver need
to know the number of arguments.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The zynqmp_firmware node has sub-nodes for the various APIs to expose
the platform management, as e.g. clock management. Therefore, the driver
must populate the subnodes to initialize these drivers.
Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Move pxa_clear_reset_source() declaration to a header file where the
file implementing it can see it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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sha256_glue.h is not being unsed in the tree. Remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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sha256_export and sha256_import are not used in the tree. remove them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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barebox_arm_reset_vector() is a global function but we never provided a
prototype anywhere. The prototypes differ for the different boards, so
to provide a common prototype we must harmonize them.
void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
Should be suitable for all boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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external nand boot on i.MX21 depends on broken for a long time no.
As noone cared we remove it now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Many files in the tree implement functions, but do not include the
header files which provide the prototypes for these functions. This
means conflicting prototypes remain undetected. Add the missing
includes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Many functions are only used locally but still are globally visible.
Make these function static. Avoids warnings generated with -Wmissing-prototypes
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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lsee takes a loff_t pos argument and not a off_t argument. Fix.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since __imx_cpu_type won't be initialized until
imx_init()@postcore_initcall is executed cpu_is_mx8mq() will only work
correctly at core_initcall level so long as imx_cpu_type does not
resolve into __imx_cpu_type. This is currently the case and
imx8mq_init_syscnt_frequency() works as expected, but it probably
won't be in the future.
To avoid this problem introduce imx8mq_cpu_lowlevel_init() and do
system counter frequency initialization there. Also convert all of the
i.MX8MQ boards to use this new function.
Fixes: 5691aed9a ("ARM: i.MX8MQ: Check CPU type in imx8mq_init_syscnt_frequency()")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We need to make sure that CNTFRQ is initialized before corresponding
clocksource driver tries to use it, otherwise we'll end up crashing
due to division by zero.
We can't convert imx7_timer_init() to be an initcall since it is an
i.MX7 specific task, but CPU type information won't be availible until
after imx_init() gets executed at postcore_initcall() level. To solve
this move all of the necessary code to be a part of
imx7_cpu_lowlevel_init().
Note, that original code both hardcoded frequency value to 8MHz as
well as tried to write it to the first element of the frequency mode
table which appears to be read-only on i.MX7. So while we are at it,
simplify the code by adding set_cntfrq() implementation for ARMv7 and
copy the code we already using for i.MX8MQ.
Fixes: dece70752 ("clocksource: Enable architected timer support for CPU_V7")
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds initial STMicroelectronics MP1 support along with support
for the DK2 devel board. Only very basic support:
- UART
- SDRAM memory base/size
- No 1st stage support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The generic clk divider needs clock flags and divider flags. Fix
prototypes to take both as separate arguments.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Raspberry Pi Compute Module 3+ was released in January 2019.
Source for the new board revision code:
https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
Signed-off-by: Tomaz Solc <tomaz.solc@tablix.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Based on Linux commit 8636a1f9677db4f883f29a072f401303acfc2edd
This will be needed when you sync Kconfig with Linux 5.0 or later.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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MEMGETBADBLOCK returns loff_t, so that's the type we should use to
store its result.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Don't use 'int' to store lseek()'s return value to avoid problems with
large seek offsets. While at it, make sure to populate return error
code from 'errno'.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Don't use 'int' to store lseek()'s return value to avoid problems with
large seek offsets. While at it, make sure to populate return error
code from 'errno'.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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MEMGETBADBLOCK returns loff_t, so that's the type we should use to
store its result.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Open_and_lseek() return actual error code via errno, so change the
code to use it instead of return value.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the TQ TQMLS1046a board. Currently supported:
- UART
- SD/MMC
- Network on eth3, eth2 currently not working for unknown reasons
First stage support exists but is currently untested. Serdes ports are
not yet supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The RDB is the Freescale LS1046a reference board. This patch adds
support for it. Currently supported:
- DDR4 RAM as read from SPD EEPROM
- UART
- SD/MMC
- RGMII network ports
The Serdes ports are currently not supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the clock controller found on Layerscape
SoCs. This is mostly an adoption of the corresponding Linux
driver. This is tested on the LS1046a SoC. Other ARM based Layerscape
SoCs should work aswell, support for the PowerPC based SoCs has
been removed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds basic Layerscape support:
- Makefile/Kconfig
- Register maps
- errata workarounds
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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PBL often needs a way to udelay execution. Since we have a generic timer
in ARMv8 we can implement a generic udelay.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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PBL images are often constrained in size by limitations exposed by
the SoCs SRAM size or partition sizes on the boot device. So far
we tried to configure these limits in Kconfig, but with PBL multi
images and thus different limitations for the different supported
images this no longer works. This patch has another approach for
it:
During build time make variables containing the relevant sizes for
each image are created. These are:
PBL_CODE_SIZE_$(symbol)
PBL_MEMORY_SIZE_$(symbol)
PBL_IMAGE_SIZE_$(symbol)
PBL_CODE_SIZE_$(symbol) contains the pure code size of the PBL, it
should be smaller than the available SRAM during boot. Normally the
PBL's bss segment also needs to be in the initial SRAM, for this
case PBL_MEMORY_SIZE_$(symbol) is the relevant variable.
PBL_IMAGE_SIZE_$(symbol) contains the full size of the PBL image
including the compressed payload (but without any image headers
created later by SoC specific image tools).
$(symbol) is a placeholder for the start symbol used for this PBL image,
thus for the i.MX53 QSB with entry start_imx53_loco
PBL_CODE_SIZE_start_imx53_loco
will be created. The images/Makefile.* can use these variables directly
to check sizes or specify the same variables with a "MAX_" prefix. So
when images/Makefile.imx specifies
MAX_PBL_CODE_SIZE_start_imx53_loco = 0x10000
then the build system will make sure that the PBL code for the QSB will
not get bigger than 64KiB.
Also included in this patch are the size restrictions for the i.MX8MQ
images as an example how to use this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The i210 on the RDU3 must be configured in the same way as on RDU2.
Move the config check/patching to the common directory and add the
compatible of the RDU3 boards.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The current defaultenv-kindle-mx50 requires MCI_STARTUP to boot the installed
linux. CMD_LOADY is mentioned in the doc for barebox update purposes.
FS_EXT4, FS_FAT and FS_FAT_WRITE gives users file system access. Also enable
CMD_MEMTEST, CMD_CLK, CMD_REGULATOR and CMD_EDIT for interested users.
The extended image will consume 195kB of available 253kB.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Without the pullups enabled, the GPIO change after a button release
took some hundered milliseconds.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With the MMU enabled, a memtest runs 14 times faster.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add watchdog support for imx8mq-phytec-phycore-som.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patches the DSA switch config in the kernel DT if the unit is
a 12.1" one, which doesn't have the FEC wired up to the switch.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
[andrew.smirnov@gmail.com: Ported the patch to use p/n fixups]
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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RDU1 devices come in different varietes and, depending on
particular configuration, certain device tree nodes need to be
adjusted accoringly.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On both RDU1 and RDU2 the seat notwork configuration is stored in
a configuration EEPROM accessible via the RAVE SP. Add an initcall
to fetch this configuration and add it to the kernel command line.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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