summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* ARM: aarch64: do not use 32bit optimized find bit functionsMichael Tretter2019-05-062-0/+9
| | | | | | | | | | | | | | | | The optimized find bit functions are only implemented for 32 bit and are not built on aarch64 systems. Therefore, for example bootchooser cannot be build for aarch64. Select the generic find_bit implementations on aarch64. As the decision, if lib64 or lib32 is build or not, directly depends on CPU_V8, the generic implementation also should be used if CPU_V8 is selected. Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zii-imx8mq-dev: select ZII_COMMONLucas Stach2019-05-061-0/+1
| | | | | | | | | The RDU3 shares some of the board fixups with the other Zii boards. For those to work ZII_COMMON needs to be enabled. Fixes: d76ba38a1605 (ARM: zii-common: reuse i210 config check for RDU3) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: disable IPU QoS setup for correct SoCsRouven Czerwinski2019-05-061-1/+1
| | | | | | | | | | | | | | | | | | The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL"), but instead it bails at the Solo, not the SX and SL. The original intent was most probably to add an exception for the i.MX6 Solo as well, so everything else is skipped, including the SX, SL and now the UL and ULL. Fix the code to reflect this. On the SX, SL, UL, ULL, this now avoids writes to memory, which isn't described in the datasheets. On the S, it now configures the QoS settings. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynqmp'Sascha Hauer2019-04-095-2/+177
|\
| * ARM: zynqmp: switch to firmware clock driverMichael Tretter2019-03-182-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | In the device tree, the clock controller is a subnode of the firmware node. Devices refer to the clocks by an id that is shared between the ATF and the driver. While the bindings for the clock controller are already upstream, the device in mainline Linux does not use them, yet. Add them in the Barebox device tree for now. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: add firmware DT nodeThomas Haemmerle2019-03-182-0/+18
| | | | | | | | | | | | | | | | | | Add firmware DT node in ZynqMP device tree. This node uses bindings as per new firmware interface driver. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: move PAYLOAD_ARG_CNT to firmware headerMichael Tretter2019-03-182-2/+2
| | | | | | | | | | | | | | | | In order to use the query() call, the users of the firmware driver need to know the number of arguments. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: populate zynqmp_firmware dt nodeThomas Haemmerle2019-03-181-0/+1
| | | | | | | | | | | | | | | | | | | | The zynqmp_firmware node has sub-nodes for the various APIs to expose the platform management, as e.g. clock management. Therefore, the driver must populate the subnodes to initialize these drivers. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/warnings'Sascha Hauer2019-04-0991-161/+122
|\ \
| * | ARM: PXA: Provide prototype for pxa_clear_reset_source()Sascha Hauer2019-03-182-2/+4
| | | | | | | | | | | | | | | | | | | | | Move pxa_clear_reset_source() declaration to a header file where the file implementing it can see it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: sha256: Remove unused header fileSascha Hauer2019-03-181-23/+0
| | | | | | | | | | | | | | | | | | sha256_glue.h is not being unsed in the tree. Remove it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: sha256: Remove unused functionsSascha Hauer2019-03-181-18/+0
| | | | | | | | | | | | | | | | | | sha256_export and sha256_import are not used in the tree. remove them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: boards: Harmonize barebox_arm_reset_vector() prototypeSascha Hauer2019-03-1861-67/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox_arm_reset_vector() is a global function but we never provided a prototype anywhere. The prototypes differ for the different boards, so to provide a common prototype we must harmonize them. void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) Should be suitable for all boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: external-nand-boot: remove unused i.MX21 entrySascha Hauer2019-03-181-3/+0
| | | | | | | | | | | | | | | | | | | | | external nand boot on i.MX21 depends on broken for a long time no. As noone cared we remove it now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | treewide: Add missing includesSascha Hauer2019-03-1814-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Many files in the tree implement functions, but do not include the header files which provide the prototypes for these functions. This means conflicting prototypes remain undetected. Add the missing includes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | treewide: Make locally used functions staticSascha Hauer2019-03-1816-47/+32
| | | | | | | | | | | | | | | | | | | | | Many functions are only used locally but still are globally visible. Make these function static. Avoids warnings generated with -Wmissing-prototypes Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: semihosting: Fix function prototypeSascha Hauer2019-03-181-1/+1
| | | | | | | | | | | | | | | | | | lsee takes a loff_t pos argument and not a off_t argument. Fix. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/stm32'Sascha Hauer2019-04-0924-62/+359
|\ \ \
| * | | ARM: i.MX8MQ: Don't use cpu_is_mx8mq() at core_initcall levelAndrey Smirnov2019-03-186-25/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since __imx_cpu_type won't be initialized until imx_init()@postcore_initcall is executed cpu_is_mx8mq() will only work correctly at core_initcall level so long as imx_cpu_type does not resolve into __imx_cpu_type. This is currently the case and imx8mq_init_syscnt_frequency() works as expected, but it probably won't be in the future. To avoid this problem introduce imx8mq_cpu_lowlevel_init() and do system counter frequency initialization there. Also convert all of the i.MX8MQ boards to use this new function. Fixes: 5691aed9a ("ARM: i.MX8MQ: Check CPU type in imx8mq_init_syscnt_frequency()") Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX7: Make sure CNTFRQ is initialized early enoughAndrey Smirnov2019-03-183-35/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to make sure that CNTFRQ is initialized before corresponding clocksource driver tries to use it, otherwise we'll end up crashing due to division by zero. We can't convert imx7_timer_init() to be an initcall since it is an i.MX7 specific task, but CPU type information won't be availible until after imx_init() gets executed at postcore_initcall() level. To solve this move all of the necessary code to be a part of imx7_cpu_lowlevel_init(). Note, that original code both hardcoded frequency value to 8MHz as well as tried to write it to the first element of the frequency mode table which appears to be read-only on i.MX7. So while we are at it, simplify the code by adding set_cntfrq() implementation for ARMv7 and copy the code we already using for i.MX8MQ. Fixes: dece70752 ("clocksource: Enable architected timer support for CPU_V7") Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add initial STM32MP1 supportSascha Hauer2019-03-1315-0/+307
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial STMicroelectronics MP1 support along with support for the DK2 devel board. Only very basic support: - UART - SDRAM memory base/size - No 1st stage support Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clocksource: Enable architected timer support for CPU_V7Sascha Hauer2019-03-111-0/+19
| | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: divider: pass divider flagsSascha Hauer2019-03-111-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | The generic clk divider needs clock flags and divider flags. Fix prototypes to take both as separate arguments. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/misc'Sascha Hauer2019-04-0910-41/+44
|\ \ \
| * | | ARM: rpi: add board revision for Compute Module 3+Tomaz Solc2019-03-272-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Raspberry Pi Compute Module 3+ was released in January 2019. Source for the new board revision code: https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md Signed-off-by: Tomaz Solc <tomaz.solc@tablix.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | treewide: surround Kconfig file paths with double quotesMasahiro Yamada2019-03-218-40/+40
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Based on Linux commit 8636a1f9677db4f883f29a072f401303acfc2edd This will be needed when you sync Kconfig with Linux 5.0 or later. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/lseek'Sascha Hauer2019-04-083-10/+14
|\ \ \
| * | | ARM: i.MX: bbu: Fix variable type in imx_bbu_internal_v2_write_nand_dbbt()Andrey Smirnov2019-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MEMGETBADBLOCK returns loff_t, so that's the type we should use to store its result. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: bbu: Fix lseek error check in imx_bbu_internal_v2_write_nand_dbbt()Andrey Smirnov2019-03-111-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't use 'int' to store lseek()'s return value to avoid problems with large seek offsets. While at it, make sure to populate return error code from 'errno'. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: bbu: Fix lseek error check in imx_bbu_external_nand_update()Andrey Smirnov2019-03-111-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't use 'int' to store lseek()'s return value to avoid problems with large seek offsets. While at it, make sure to populate return error code from 'errno'. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: bbu: Fix variable type in imx_bbu_external_nand_update()Andrey Smirnov2019-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MEMGETBADBLOCK returns loff_t, so that's the type we should use to store its result. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | MIPS: ath79: Use errno to get error code from open_and_lseek()Andrey Smirnov2019-03-111-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | Open_and_lseek() return actual error code via errno, so change the code to use it instead of return value. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/layerscape'Sascha Hauer2019-04-0849-1/+2278
|\ \ \
| * | | ARM: Add layerscape_defconfigSascha Hauer2019-03-131-0/+111
| | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Layerscape: Add TQ TQMLS1046a board supportSascha Hauer2019-03-1318-0/+888
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the TQ TQMLS1046a board. Currently supported: - UART - SD/MMC - Network on eth3, eth2 currently not working for unknown reasons First stage support exists but is currently untested. Serdes ports are not yet supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Layerscape: Add LS1046a RDB board supportSascha Hauer2019-03-1317-0/+464
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RDB is the Freescale LS1046a reference board. This patch adds support for it. Currently supported: - DDR4 RAM as read from SPD EEPROM - UART - SD/MMC - RGMII network ports The Serdes ports are currently not supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | clk: Add Layerscape clk supportSascha Hauer2019-03-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the clock controller found on Layerscape SoCs. This is mostly an adoption of the corresponding Linux driver. This is tested on the LS1046a SoC. Other ARM based Layerscape SoCs should work aswell, support for the PowerPC based SoCs has been removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add basic Layerscape supportSascha Hauer2019-03-1312-0/+777
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic Layerscape support: - Makefile/Kconfig - Register maps - errata workarounds Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | esdhc-xload: Add support for LayerscapeSascha Hauer2019-03-131-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add arm64 pbl udelaySascha Hauer2019-03-132-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PBL often needs a way to udelay execution. Since we have a generic timer in ARMv8 we can implement a generic udelay. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | pbl multiimage: Allow to check image sizesSascha Hauer2019-03-132-0/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PBL images are often constrained in size by limitations exposed by the SoCs SRAM size or partition sizes on the boot device. So far we tried to configure these limits in Kconfig, but with PBL multi images and thus different limitations for the different supported images this no longer works. This patch has another approach for it: During build time make variables containing the relevant sizes for each image are created. These are: PBL_CODE_SIZE_$(symbol) PBL_MEMORY_SIZE_$(symbol) PBL_IMAGE_SIZE_$(symbol) PBL_CODE_SIZE_$(symbol) contains the pure code size of the PBL, it should be smaller than the available SRAM during boot. Normally the PBL's bss segment also needs to be in the initial SRAM, for this case PBL_MEMORY_SIZE_$(symbol) is the relevant variable. PBL_IMAGE_SIZE_$(symbol) contains the full size of the PBL image including the compressed payload (but without any image headers created later by SoC specific image tools). $(symbol) is a placeholder for the start symbol used for this PBL image, thus for the i.MX53 QSB with entry start_imx53_loco PBL_CODE_SIZE_start_imx53_loco will be created. The images/Makefile.* can use these variables directly to check sizes or specify the same variables with a "MAX_" prefix. So when images/Makefile.imx specifies MAX_PBL_CODE_SIZE_start_imx53_loco = 0x10000 then the build system will make sure that the PBL code for the QSB will not get bigger than 64KiB. Also included in this patch are the size restrictions for the i.MX8MQ images as an example how to use this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2019-04-0821-514/+1075
|\ \ \
| * | | ARM: zii-common: reuse i210 config check for RDU3Lucas Stach2019-03-272-29/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i210 on the RDU3 must be configured in the same way as on RDU2. Move the config check/patching to the common directory and add the compatible of the RDU3 boards. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: i.MX: extend kindle-mx50 defconfigAlexander Kurz2019-03-181-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current defaultenv-kindle-mx50 requires MCI_STARTUP to boot the installed linux. CMD_LOADY is mentioned in the doc for barebox update purposes. FS_EXT4, FS_FAT and FS_FAT_WRITE gives users file system access. Also enable CMD_MEMTEST, CMD_CLK, CMD_REGULATOR and CMD_EDIT for interested users. The extended image will consume 195kB of available 253kB. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM Kindle3: switch on pull-ups for fiveway deviceAlexander Kurz2019-03-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without the pullups enabled, the GPIO change after a button release took some hundered milliseconds. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM Kindle3 defconfig: enable MMUAlexander Kurz2019-03-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the MMU enabled, a memtest runs 14 times faster. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: dts: mx8mq-phytec-phycore-som: Add watchdogChristian Hemp2019-03-181-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add watchdog support for imx8mq-phytec-phycore-som. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: rdu2: patch DSA configAndrey Smirnov2019-03-181-2/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches the DSA switch config in the kernel DT if the unit is a 12.1" one, which doesn't have the FEC wired up to the switch. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> [andrew.smirnov@gmail.com: Ported the patch to use p/n fixups] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: rdu2: Add p/n based fixups for touchscreen and display panelLucas Stach2019-03-182-1/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RDU1 devices come in different varietes and, depending on particular configuration, certain device tree nodes need to be adjusted accoringly. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: zii-common: fetch network config from SPLucas Stach2019-03-182-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On both RDU1 and RDU2 the seat notwork configuration is stored in a configuration EEPROM accessible via the RAVE SP. Add an initcall to fetch this configuration and add it to the kernel command line. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>