| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Update handler returned the written bytes of the partition table on success
instead of 0. Return 0 or error code now.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since 7ba0f2d299 arm_create_pte() flushes the page table entries itself
and it's no longer done in arch_remap_range(). Unfortunately it does
not flush the modified 1st level page table entry, but instead the base
of the page table. Fix it up.
Fixes: 7ba0f2d299 ARM: mmu: fix cache flushing when replacing a section with a PTE
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Previously the FPGA was configured externally on the Achilles. On newer versions
this is changed and barebox has to configure the FPGA before the SDRAM can be
used.
If the FPGA is configured via JTAG or from an external memory, the *-bringup
version can be used.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Some Arria10 boards don't have the FPGA programmed externally.
Instead barebox needs to do that. As the Arria10 has the SDRAM
controller in the FPGA, the first thing we need to do is,
configure the FPGA before the SDRAM can even be used.
It works like this:
1. boot ROM fetches the PBL from MMC
2. read the MBR from MMC (this depends on the setup done by the boot ROM)
3. read the Bitstream from the MMC and program the FPGA
4. re-read the barebox image from MMC, this time with the full barebox
that is appended to the PBL
5. jump into the full barebox
Only supported boot device is eMMC.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Arria10 init code resets all peripherals. Convert this to keep the bootmedium
out of reset and keep the setup done by the boot ROM.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The newer dtc has stricter checks on devicetrees. Fix the warnings.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Move the setup of the shared- and fpgapins to its own function.
These pins can only be configured and let out of reset after the FPGA has been
programmed.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Instead of copy+pasting the debug_ll messages to every new board,
move them to the respective functions.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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A prebootloader image might also contain a fully working barebox and
allows to be booted second stage. Thus we add a handler here to give it
a try.
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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After the PCIe switch has been scanned its GPIOs need to be
configured as output-high to release the devices behind the
switch from their reset state and make them discoverable to
the bus scan.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This is a cut down version of the Linux kernel PCI quirk infrastructure,
which allows to register and execute some fixups before the driver is
loaded.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Reset reason bits and their meaning seem to be identical between i.MX7
and i.MX8MQ. Share the definitions for the former and used it for the
latter.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For both SoCs data found in SBMR registers reflects only the boot
source that was selected via pins of fuses and not the final boot
source that ended up being used by MaskROM code. Original i.MX7 boot
source detection implementation worked around that fact by having a
special code to correctly handle "Manufacturing Mode".
MaskROM in i.MX8MQ changed what SoC uses as recovery device and
switched it to be USDHC2. It also made recovery device switch always
enabled. Since correct actual boot source detection is important to
being able to properly boot i.MX8MQ (due to not using DCD to
initialize RAM), change the code to handle described exception.
Instead of trying to adapt original i.MX7 code with yet another
special case if(), change the whole thing to do what U-Boot does on
i.MX7 and i.MX8MQ and use "Boot information for software" provided by
recent (found in i.MX7 and i.MX8MQ) versions of MaskROM.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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CPU revision information is needed for boot source detection, so
expose it as a small helper function and convert existing code to use
it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Declare ar8031_phy_fixup as static since it is not being exported to
any other users.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There's no reason for that function to be non-static, so convert it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add a cosmetic newline to the beginning of the error banner printed
when we encounter unidentified board type. This way we'd avoid
artifacts like:
barebox@ZII RDU1 Board:/ >*********************************
* Unknown system type: 00000004
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Since 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:
CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable
Implement the suggested workaround by setting the IBE bit in the
auxiliary control register, which allows the kernel to flush the
BTB properly.
Based on commit 7b37a9c732bf ("ARM: Introduce ability to enable ACR::IBE
on Cortex-A8 for CVE-2017-5715") from U-Boot.
With this patch applied the kernel now reports:
CPU0: Spectre v2: using BPIALL workaround
Tested on a imx51 babbage.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Roland Hieber <r.hieber@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add some notes on how the boot-flow goes while I still remember it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Allow placing image to align its entry point with a particular entry
point address. This is needed for SoC's like i.MX8M where
vendor-provided ARM Trusted Firmware blob will exit at specific
pre-determined address and we need to be able to pick execution up
from there.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Convert esdhc_start_image() to use constants and data types from
<mach/imx-header.h>. Also, while at it, define a simple inline
function to test if an arbitrary binary blob is i.MX flash header v2.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Move i.MX header definitions from scripts to mach-imx in order to make
it available to both script and bootloader code.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add imx8mq_atf_load_bl31() containing all of the code needed to load
and transfer control to BL31 ATF blob on i.MX8M.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We only can (and should only need to) configure cntfrq when running in
EL3 and executing this code in any other exception level will result
in exception.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Port SMCCC code from Linux kernel. To accomodate that:
- Introduce CONFIG_ARM_SMCCC, to allow enabling the code
independent of CONFIG_ARM_SECURE_MONITOR
- Bring <linux/arm-smccc.h> in
- Add necessary constants to arch/arm/asm-offsets.c
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Previous version of DDR initialization code was generated by a beta
version of MX8_DDR_tool. This updates the code to the output of
MX8_DDR_tool v1.0, which seem to fix the vendor Linux kernel hang*
that was happening with the previous version.
* The kernel would hang as soon as it tried to utilize DDR's DVFS
features and switch DDR frequency (disabling busfreq-imx8mq.c would
fix the problem).
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make a static inline wrapper actually static inline.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Not sure why it was working before, but with recent update of AArch64
GCC to 8.1.1 on my Fedora 28 machine, compiling barebox_arm_entry()
yields the following assembly:
0000000000002aac <barebox_arm_entry>:
2aac: a9bd7bfd stp x29, x30, [sp, #-48]!
2ab0: d1404023 sub x3, x1, #0x10, lsl #12
2ab4: d1004063 sub x3, x3, #0x10
2ab8: 910003fd mov x29, sp
2abc: 8b000063 add x3, x3, x0
2ac0: a90153f3 stp x19, x20, [sp, #16]
2ac4: aa0003f3 mov x19, x0
2ac8: aa0103f4 mov x20, x1
2acc: f90017e2 str x2, [sp, #40] <-- storing 'boarddata' on old stack
2ad0: 9100007f mov sp, x3 <-- setting up new stack
2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate>
2ad8: f94017e2 ldr x2, [sp, #40] <--- sadness
2adc: aa1403e1 mov x1, x20
2ae0: aa1303e0 mov x0, x19
2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start>
Which result in AArch64 image (i.MX8MQ) not being bootable. With SP
marked as clobbered, the above assembly changes to the following:
0000000000002aac <barebox_arm_entry>:
2aac: a9bd7bfd stp x29, x30, [sp, #-48]!
2ab0: d1404023 sub x3, x1, #0x10, lsl #12
2ab4: d1004063 sub x3, x3, #0x10
2ab8: 910003fd mov x29, sp
2abc: a90153f3 stp x19, x20, [sp, #16]
2ac0: 8b000063 add x3, x3, x0
2ac4: aa0003f3 mov x19, x0
2ac8: aa0103f4 mov x20, x1
2acc: f90017a2 str x2, [x29, #40]
2ad0: 9100007f mov sp, x3
2ad4: 97ffffdd bl 2a48 <arm_early_mmu_cache_invalidate>
2ad8: f94017a2 ldr x2, [x29, #40]
2adc: aa1403e1 mov x1, x20
2ae0: aa1303e0 mov x0, x19
2ae4: 940000a1 bl 2d68 <barebox_multi_pbl_start>
now x29 is used to access stored x2 which avoids the problem and
allows the system to boot correctly.
The change is a no-op on AArch32.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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IS_ENABLED has to be passed the full symbol name including the CONFIG_
prefix. Otherwise IS_ENABLED evaluates to 0.
Fixes: 2877e08f9e1a ("ARM: phytec-som-am335x: Add autoenable")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
--
Cc: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Make a static inline wrapper actually static inline.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When replacing a section with a PTE, we must make sure that the newly
initialized PTE entries are flushed from the cache before changing the
entry in the TTB. Otherwise a L1 TLB miss causes the hardware pagetable
walker to walk into a PTE with undefined content, causing exactly that
behaviour.
Move all the necessary cache flushing to arm_create_pte(), to avoid any
caller getting this wrong in the future.
Fixes: e3e54c644180 (ARM: mmu: Implement on-demand PTE allocation)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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A NO_PAD_CTRL flag used to keep a pad configuration untouched.
With commit 094820a63bfd ("i.MX: iomuxv3: Use helper functions in iomux-v3.h")
the NO_PAD_CTRL semantic changed to set a pad configurations to zero, which
breaks non-DT boards, where NO_PAD_CTRL is freqently used to keep a boot-up
default pad configuration, which often is non zero.
Restore the old semantic, dont write PAD_CTRL when NO_PAD_CTRL is set.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Fixes: e3e54c6441 ARM: mmu: Implement on-demand PTE allocation
PGD_FLAGS_WC_V7 lacks the PMD_TYPE_SECT and PMD_SECT_BUFFERABLE flags.
Without them a dma_alloc_writecombine() creates an invalid section when
it crosses a section boundary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
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