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* Merge branch 'for-next/layerscape'Sascha Hauer2019-05-1018-170/+365
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| * ARM: Layerscape: Add device tree compatible to image metadataSascha Hauer2019-05-102-0/+6
| | | | | | | | | | | | | | Enrich the image metadata with the device tree compatible string the image supports. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Add environment and update handlersSascha Hauer2019-05-102-0/+80
| | | | | | | | | | | | | | The TQMLS1046a can boot from QSPI and SD/MMC. Add partitioning for these devices and barebox environment / barebox update handlers on them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Support booting from QSPISascha Hauer2019-05-101-1/+1
| | | | | | | | | | | | | | | | | | We have to build correct images suitable for QSPI, thus have to call lspbl_spi_image instead of lspbl_image. In lowlevel code call the xload function which detects the bootsource rather than hardcoding SD/MMC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: unify pbi filesSascha Hauer2019-05-102-33/+2
| | | | | | | | | | | | | | | | | | | | | | This unifies the two different pbi files. With our approach for QSPI booting differences in the pbi files are not necessary: - We do not do execute in place for QSPI, so we do not need different image execution addresses - Setting up the QSPI clock doesn't hurt even for SD boot Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: print life signs when debuggingSascha Hauer2019-05-101-1/+5
| | | | | | | | | | | | | | | | Do the UART initialization after the SoC specific lowlevel setup and print the usual '>' when early debuging is enabled. To let this go out properly it seems we have to wait a small amount of time beforehand. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Sync qspi RCW from TQ U-BootSascha Hauer2019-05-101-4/+4
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: configure qspi dividerSascha Hauer2019-05-101-0/+3
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: ls1046a: Add bbu handlersSascha Hauer2019-05-101-0/+22
| | | | | | | | | | | | | | The barebox images can simply be written to the partitions, so we can use bbu_register_std_file_update() for updating to MMC and QSPI. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: ls1046a: Add automatic bootsource detection xload functionSascha Hauer2019-05-103-1/+27
| | | | | | | | | | | | | | Add a helper function which continues booting from the detected boot source. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: Add QSPI boot supportSascha Hauer2019-05-103-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting Layerscape from QSPI is a bit tricky and the approach we take is different from the one U-Boot has taken, so it's worth writing and reading the following explanation. The QSPI controller can map the Flash contents into the memory space (On LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this memory window. The Layerscape SoCs have a PowerPC history, so it seemed appropriate for the designers to let the QSPI controller operate in big endian mode by default. To let the SoC see the correct RCW we have to write the RCW and PBI data with be64 endianess. Our PBL image tool pokes the initial binary into the SoC internal SRAM using PBI data as done with SD/MMC boot aswell. barebox then changes the QSPI controller endianess to le64 to properly read the barebox binary (placed at an flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and jumps to it. U-Boot has another approach. Here the initial binary is executed in place directly at 0x40100000. This means the QSPI controller endianess must be swapped inside the PBI data. This has the effect that the whole RCW/PBI data must be 64bit endianess swapped *except* the very last word of the PBI data which contains the CRC command and is read already with changed endianess. As a conclusion when porting QSPI PBI files from U-Boot to barebox skip commands changing the endianess in the QSPI controller and make sure the image is executed in internal SRAM and not in the Flash memory window. Lines like this should be removed: 09550000 000f400c This sets the binary execution address: 09570604 40100000 For barebox it should be changed to 0x10000000. As a result the PBI files can probably be unified between SD and QSPI boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: ls1046a: Add bootsource detection supportSascha Hauer2019-05-103-0/+42
| | | | | | | | | | | | Not much to do, there are only a few boot sources supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: defconfig: Enable more featuresSascha Hauer2019-05-091-1/+7
| | | | | | | | | | | | | | | | The TQMLS1046a has an i2c mux and a i2c gpio expander. Add support for it and also disable early debugging as these are for a single board only. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Fix pinmux setup for i2c4Sascha Hauer2019-05-081-0/+6
| | | | | | | | | | | | With this the I2C mux on i2c4 works properly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Unify SD and eMMC imagesSascha Hauer2019-05-082-91/+7
| | | | | | | | | | | | | | TQ has unified SD and eMMC images in their U-Boot. Do the same in barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Update device tree files from tq repositorySascha Hauer2019-05-082-25/+46
| | | | | | | | | | | | Update TQMLS1046a device tree files from TQ repository as of rocko.TQMLS1046A.BSP.SW.0002 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Use static DDR settingsSascha Hauer2019-05-081-14/+68
| | | | | | | | | | | | | | TQ prefers static values in their U-Boot, so use these values in barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: Layerscape: TQMLS1046a: Set cpo_sample valueSascha Hauer2019-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | Starting the board issues the warning: WARN: pls set popts->cpo_sample = 0x48 So set the value to the desired value. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2019-05-1010-33/+34
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| * | ARM: zii-vf610-dev: Add ZII SSMB DTU boardAndrey Smirnov2019-04-264-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | Add the Zodiac Digital Tapping Unit, a VF610 based network device with 5 Ethernet ports. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: zii-imx8mq-dev: Drop unnecessary barrier() in switch statementAndrey Smirnov2019-04-231-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AArch64 uses PC-relative addressing instead of absolute one for data lookups, so compiling switch statement into a LUT shouldn't be a problem regardless if relocation happened or not. Disassembly of PBL code looks almost exactly the same with or without this workaround, so it is clearly not needed. Drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: zii-imx51-rdu1: Use -fno-tree-switch-conversion -fno-jump-tablesAndrey Smirnov2019-04-232-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original and very poor workaround no longer works against GCC8, so drop it and replace with a proper solution that should've been used in the first place - specifying -fno-tree-switch-conversion -fno-jump-tables as CFLAGS when building lowlevel.c Tested to work with: - GCC 8.2.1 (arm-none-eabi) - GCC 7.1.0 (arm-none-eabi) - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: zii-vf610-dev: Use -fno-tree-switch-conversion -fno-jump-tablesAndrey Smirnov2019-04-232-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original and very poor workaround no longer works against GCC8, so drop it and replace with a proper solution that should've been used in the first place - specifying -fno-tree-switch-conversion -fno-jump-tables as CFLAGS when building lowlevel.c Tested to work with: - GCC 8.2.1 (arm-none-eabi) - GCC 7.1.0 (arm-none-eabi) - GCC 4.8.4 (armv7l-timesys-linux-gnueabihf) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: imx8mq: link PCIE1 and PCIE2 power domainsLucas Stach2019-04-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those two power domains can only be used together. The link between the two has been dropped with the dts merge of v5.1-rc1. Fix this. Fortunately the i.MX8MQ PCIe support will land in Linux 5.2, so we can drop all those PCIe related local DT overrides with the next big dts upstream sync. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX25: Add some more clocksSteffen Trumtrar2019-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some clocks needed for: - RNGB - SCC - Dryice RTC Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/ctrlc'Sascha Hauer2019-05-101-1/+1
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| * | | Shell: Handle aborting loops betterSascha Hauer2019-04-241-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's easy to get stuck in an infinite loop in the hush shell: while true; do sleep 1; done The 'sleep' command will check for ctrl-c with the ctrlc() function. This will abort the sleep command. Hush then checks for ctrl-c again in the loop. The ctrl-c in the buffer has already been eaten by the sleep command, so the loop will continue. With this patch we remember the presence of a ctrl-c character in a variable instead of checking for a new character each time. The variable must be resetted explicitly by calling ctrlc_handled() which will be called by the shell in the outer loop. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/arm'Sascha Hauer2019-05-106-11/+80
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| * | ARM: mmu: mark uncached regions as eXecute never on v7Ahmad Fatoum2019-04-293-9/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Cortex-A Series Programmer's Guide notes[1]: > When set, the Execute Never (XN) bit in the translation table entry > prevents speculative instruction fetches taking place from desired > memory locations and will cause a prefetch abort to occur if execution > from the memory location is attempted. > > Typically device memory regions are marked as execute never to prevent > accidental execution from such locations, and to prevent undesirable > side-effects which might be caused by speculative instruction fetches. Heed the advice and mark uncached memory with the XN bit, when the CPU is >=v7. It's possible that there are SoCs that have a section shared between device memory and the on-chip RAM hosting the PBL. In such a section, every page except for the OCRAM's should be mapped XN, but as we know of no SoC with such an OCRAM layout, we ignore this possibility for now and let mmu_early_enable map sections only. [1]: 9.6.3 "Execute Never", Version 4.0 Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: mmu: remove doubly defined macroAhmad Fatoum2019-04-291-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | PMD_SECT_DEF_CACHED is defined along with PMD_SECT_DEF_UNCACHED in mmu.h, which is included two lines prior. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: cache-armv7: start invalidation from outer levelsAhmad Fatoum2019-04-291-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 25/4/19 11:57, Lucas Stach wrote: > [T]he sequence that could go wrong in Barebox is as follows: > 1. CPU core starts invalidating at L1 cache level > 2. HW prefetcher decides that a specific address should be brought into > the L1 cache. > 3. HW prefetcher finds a valid block for the requested address in L2 > cache and moves cached data from L2 to L1. > 4. Only now CPU core invalidates L2 cache. > > In the above sequence we now have invalid data in the L1 cache line. > The correct sequence will avoid this issue: > > 1. CPU core starts invalidating at L2 cache level > 2. HW prefetcher decides that a specific address should be brought into > the L1 cache. > 3. HW prefetcher sees invalid tags for the requested address in L2 > cache and brings in the data from external memory. > 4. CPU core invalidates L1 cache, discarding the prefetched data. > The ARM Cortex-A Series Programmer's Guide addresses this issue in the SMP-context[1]: > If another core were to access the affected address between those > two actions, a coherency problem can occur. Such problems can be avoided > by following two simple rules. > > * When cleaning, always clean the innermost (L1) cache first and then > clean the outer cache(s). > * When invalidating, always invalidate the outermost cache first and > the L1 cache last. The current code correctly iterates from inner to outer cache levels when flushing/cleaning (r8 == 0), invalidation (r8 == 1) occurs in the same direction though. Adjust the invalidation iteration order to start from the outermost cache instead. Equivalent C-Code: enum cache_op { CACHE_FLUSH = 0, CACHE_INVAL = 1 }; register enum cache_op operation asm("r8"); register int i asm("r12"); register int limit asm("r3") = max_cache_level << 1; // e.g. 4 with L2 max +if (operation == CACHE_FLUSH) { i = 0; +} else { + i = limit - 2; +} bool loop_again; do { /* [snip] */ + if (operation == CACHE_FLUSH) { i += 2; loop_again = limit > i; + } else { + loop_again = i > 0; + i -= 2; + } } while (loop_again); [1]: 18.6 "TLB and cache maintenance broadcast", Version 4.0 Suggested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: cache-armv7: work around Cortex-A7 erratum 814220Ahmad Fatoum2019-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on 0e9a87bb from the linux-imx kernel: ------------------------------------------------------------------------------ | ARM/MP: 814220—B-Cache maintenance by set/way operations can execute | out of order. | | Description: | The v7 ARM states that all cache and branch predictor maintenance operations | that do not specify an address execute, relative to each other, in program | order. However, because of this erratum, an L2 set/way cache maintenance | operation can overtake an L1 set/way cache maintenance operation, this would | cause the data corruption. | | This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. | | This patch is the SW workaround by adding a DSB before changing cache levels | as the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation. | Signed-off-by: Jason Liu <r64343@freescale.com> ------------------------------------------------------------------------------ It was later posted to LKML for Linux inclusion, but is not yet mainline: <20190214083145.15148-1-benjamin.gaignard@linaro.org> Unlike the Linux version, we don't make the barrier dependent on a Kconfig option and always execute the dsb: On 25/4/19 12:02, Lucas Stach wrote: > I don't think we need a Kconfig option here. This function is not > really performance critical. The short pipeline stall introduced by the > dsb when switching the cache level is minor compared to the time it > takes to actually move the cache blocks on a clean. > > Just always execute the [dsb] and add a comment on why it is needed. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()Andrey Smirnov2019-04-262-0/+27
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3, SCTLR will be in a state we expect it to be. Add code to reset it to a known state, so we'd always start form clean slate. This is also matches what we've been doing non 64-bit ARMs. Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon appear to have different mask ROM behaviour where it now leaves MMU enabled if no valid boot source is found. Page table it sets up doesn't include DDR range, so trying to bootstrap the device via JTAG/OpenOCD results in an abort. The value for SCTLR_ELx_FLAGS was taken from Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: aarch64: do not use 32bit optimized find bit functionsMichael Tretter2019-05-062-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The optimized find bit functions are only implemented for 32 bit and are not built on aarch64 systems. Therefore, for example bootchooser cannot be build for aarch64. Select the generic find_bit implementations on aarch64. As the decision, if lib64 or lib32 is build or not, directly depends on CPU_V8, the generic implementation also should be used if CPU_V8 is selected. Reported-by: Thomas Hämmerle <Thomas.Haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: zii-imx8mq-dev: select ZII_COMMONLucas Stach2019-05-061-0/+1
| | | | | | | | | | | | | | | | | | The RDU3 shares some of the board fixups with the other Zii boards. For those to work ZII_COMMON needs to be enabled. Fixes: d76ba38a1605 (ARM: zii-common: reuse i210 config check for RDU3) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: imx: disable IPU QoS setup for correct SoCsRouven Czerwinski2019-05-061-1/+1
|/ | | | | | | | | | | | | | | | | | The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't execute IPU QoS setup on MX6 SX/SL"), but instead it bails at the Solo, not the SX and SL. The original intent was most probably to add an exception for the i.MX6 Solo as well, so everything else is skipped, including the SX, SL and now the UL and ULL. Fix the code to reflect this. On the SX, SL, UL, ULL, this now avoids writes to memory, which isn't described in the datasheets. On the S, it now configures the QoS settings. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynqmp'Sascha Hauer2019-04-095-2/+177
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| * ARM: zynqmp: switch to firmware clock driverMichael Tretter2019-03-182-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | In the device tree, the clock controller is a subnode of the firmware node. Devices refer to the clocks by an id that is shared between the ATF and the driver. While the bindings for the clock controller are already upstream, the device in mainline Linux does not use them, yet. Add them in the Barebox device tree for now. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: add firmware DT nodeThomas Haemmerle2019-03-182-0/+18
| | | | | | | | | | | | | | | | | | Add firmware DT node in ZynqMP device tree. This node uses bindings as per new firmware interface driver. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: move PAYLOAD_ARG_CNT to firmware headerMichael Tretter2019-03-182-2/+2
| | | | | | | | | | | | | | | | In order to use the query() call, the users of the firmware driver need to know the number of arguments. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynqmp: populate zynqmp_firmware dt nodeThomas Haemmerle2019-03-181-0/+1
| | | | | | | | | | | | | | | | | | | | The zynqmp_firmware node has sub-nodes for the various APIs to expose the platform management, as e.g. clock management. Therefore, the driver must populate the subnodes to initialize these drivers. Signed-off-by: Thomas Haemmerle <thomas.haemmerle@wolfvision.net> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/warnings'Sascha Hauer2019-04-0991-161/+122
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| * | ARM: PXA: Provide prototype for pxa_clear_reset_source()Sascha Hauer2019-03-182-2/+4
| | | | | | | | | | | | | | | | | | | | | Move pxa_clear_reset_source() declaration to a header file where the file implementing it can see it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: sha256: Remove unused header fileSascha Hauer2019-03-181-23/+0
| | | | | | | | | | | | | | | | | | sha256_glue.h is not being unsed in the tree. Remove it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: sha256: Remove unused functionsSascha Hauer2019-03-181-18/+0
| | | | | | | | | | | | | | | | | | sha256_export and sha256_import are not used in the tree. remove them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: boards: Harmonize barebox_arm_reset_vector() prototypeSascha Hauer2019-03-1861-67/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox_arm_reset_vector() is a global function but we never provided a prototype anywhere. The prototypes differ for the different boards, so to provide a common prototype we must harmonize them. void barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) Should be suitable for all boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: external-nand-boot: remove unused i.MX21 entrySascha Hauer2019-03-181-3/+0
| | | | | | | | | | | | | | | | | | | | | external nand boot on i.MX21 depends on broken for a long time no. As noone cared we remove it now. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | treewide: Add missing includesSascha Hauer2019-03-1814-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Many files in the tree implement functions, but do not include the header files which provide the prototypes for these functions. This means conflicting prototypes remain undetected. Add the missing includes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | treewide: Make locally used functions staticSascha Hauer2019-03-1816-47/+32
| | | | | | | | | | | | | | | | | | | | | Many functions are only used locally but still are globally visible. Make these function static. Avoids warnings generated with -Wmissing-prototypes Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: semihosting: Fix function prototypeSascha Hauer2019-03-181-1/+1
| | | | | | | | | | | | | | | | | | lsee takes a loff_t pos argument and not a off_t argument. Fix. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 08:21:49 +0000