| Commit message (Collapse) | Author | Age | Files | Lines |
... | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
We currently detect EFI-stubbed Linux images for ARM64 and RISC-V as
normal kernel images and would boot them that way. As these images
additionally start with MZ like normal PE executables, lets have new
filetypes for them. No functional change yet, but we can use a different
bootm handler for them in the future when boot is configured to be
EFI-enabled.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-82-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
struct barebox_arm_boarddata is a way for PBL to handover a machine
number instead of a FDT. We will reuse this mechanism to hand over EFI
image handle and system table in a later commit, so prepare for that by
moving it to a central location and adjust the naming.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-64-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
For development, it has proven very useful to be able to load the same
barebox binary both as EFI loader and EFI payload and debug the
interaction. For this to work, we need to mark all current EFI payload
initcalls as such to avoid running them when barebox is not running
as EFI payload.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-63-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
get_runtime_offset returns the offset that needs to be added onto
code addresses to arrive at the runtime address. This is 0 after code
relocation and the function calculates it by keeping a reference to _text
and substituting it from the actual _text address, which is found out in
a position-independent manner.
For enabling barebox PBL text section to be mappable W^X, we need to
avoid relocation entries within code, so let's move the runtime offset
into the data section, which is always mapped writable.
As ldr has only a 4K range for label references, we switch to ldr_l,
which has a 4G range.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-58-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The code resulting from building the barebox ARM64 assembly contains
relocations, which could've been position-independent just as well.
Let's make them truly position independent by turning:
ldr x0, =label
into
adr_l x0, label
adr_l is position independent by virtue of being implemented using adrp,
so it's usuable as-is before relocation and requires no manual addition
of get_runtime_offset().
With these changes, only relocation necessary for the ARM64 generic DT
2nd stage is the one needed for get_runtime_offset() to find out
whether barebox has been relocated.
This is one step towards supporting mapping barebox PBL text section
W^X, which precludes relocation entries emitted for code.
With this change applied, there is still a data relocation entry
in assembly code for get_runtime_offset(), but that doesn't bother us
because it's in the data section.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-57-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Kernel coding style is to usually not hide the fact that a type is a
struct or enum behind a typedef. Follow that in the EFI code.
Besides being more descriptive, this also allows forward declarations,
so <efi.h> doesn't have to be included everywhere.
No functional change.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-53-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
arm_cpu_lowlevel_init will disable the MMU, but there are valid cases to
not call it on startup, e.g. when barebox is being run as EFI payload.
To allow booting an EFI-stubbed barebox both as primary bootloader and
as EFI payload, teach mmu_early_enable() to bail out when the MMU is
already set up.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-52-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Software running under EFI can query the type of a block device. For
barebox to be able to report this, start assigning types to all block
devices it can create. No functional change yet.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-24-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
A cdev has two device tree node pointers, one directly at struct
cdev.device_node and another indirectly via cdev.dev->device_node.
We may want to remove cdev::device_node in future, but till then to
avoid users having to guess, which device_node is the correct one, add a
helper to set and get the device tree node.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-19-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The symbol is internal, so we don't break anything by renaming it.
CONFIG_EFI_PAYLOAD is clearer in intent, as BOOTUP doesn't clearly
indificate whether barebox would act as EFI payload or as EFI loader.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240304190038.3486881-9-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |_|/
|/| |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Commit 6ea731079140 ("ARM: i.MX8MQ: Streamline lowlevel startup code")
changed i.MX8MQ PBL code to mimic the code introduced for later i.MX8M
variants. The mimicry went a bit too far though and it exchanged i.MX8MQ
boot source lookup with that of the i.MX8MN. Fix this to avoid the boot
hanging with:
Unhandled bootsource BOOTSOURCE_0
Fixes: 6ea731079140 ("ARM: i.MX8MQ: Streamline lowlevel startup code")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240313144136.2157496-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
ele_call takes two arguments. The second one is removed in next where
this patch was previously applied on. Add the second argument to fix
compilation in master.
Fixes: d27c50c131 ("ARM: i.MX93: ele: start TRNG on i.MX93 rev a1")
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
On i.MX93 a0 the TRNG seems to be started automatically. On rev a1 it's
not and OP-TEE panics with "Cannot retrieve random data from ELE". Start
the TRNG to let OP-TEE startup successfully.
Link: https://lore.barebox.org/20240311080624.1836184-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|/ /
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The Raspberry Pi firmware running prior to barebox can load a kernel
directly and thus can boot barebox-dt-2nd.img straight without having to
use the Raspberry Pi images.
However, the Raspberry Pi specific PBL entry points, store the VideoCore
DT into a handover area for earlier extraction of fixups done by the
VideoCore firmware. This doesn't happen with barebox-dt-2nd.img.
Commit 5ea6e19737e1 ("raspi: support to read vc values via dt-2nd boot")
worked around this by using the barebox-internal DT, when a VideoCore DT
wasn't saved, but this in turn added a slew of warnings to the valid setup
of having no VideoCore DT at all and just using a proper Raspberry Pi
PBL with their embedded DTs:
WARNING: no property 'serial-number' found in vc fdt's '' node
no '/system' node found in vc fdt
no '/axi' node found in vc fdt
no '/hat' node found in vc fdt
no '/chosen/bootloader' node found in vc fdt
WARNING: no property 'bootargs' found in vc fdt's '/chosen' node
WARNING: no property 'overlay_prefix' found in vc fdt's '/chosen' node
WARNING: no property 'os_prefix' found in vc fdt's '/chosen' node
WARNING: 'pm_rsts' value not found in vc fdt
ERROR: Won't delete root device node
Fix this by not calling rpi_vc_fdt_parse on the barebox DT if a previous
Raspberry Pi PBL has written VIDEOCORE_FDT_ERROR into the handoff area
to indicate a missing VideoCore DT.
Fixes: 5ea6e19737e1 ("raspi: support to read vc values via dt-2nd boot")
Reported-by: Roland Hieber <rhi@pengutronix.de>
Cc: Denis Osterland-Heim <denis.osterland@gmail.com>
Link: https://lore.barebox.org/barebox/20240219191400.do7ib5rxy7tupv4i@pengutronix.de/
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240305103241.2257742-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The aarch64 bootm image handler for barebox can choose a load address
that is not 4KB aligned. This can result in unexpected behavior with
the ADRP instruction that is available in 64 bit ARM architectures.
ADRP forms a PC-relative address to a 4KB page where the bottom 12
bits of the current PC will be masked out. When the load address of
the barebox image is not 4KB aligned ADRP can end up forming an
address that starts from an invalid page of memory or the wrong page
of memory that was expected to be formed. The following patch aligns
the load address for the next barebox image to be 4KB aligned to
accommodate the ADRP instruction.
Link: https://lore.barebox.org/CAFPn3sTc_3q04koG_oPnqTmhGnejxtiva+B5KwYsCdC3czCmKw@mail.gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The PMIC is needs to be configured on the tqm93xx to properly reset the
board, see the board specific initialisation code. We had a PMIC node
in our downstream dts file which we dropped in favour for using the
upstream dts. The upstream dts doesn't have a PMIC node yet, so add it
again. We do not need the regulator subnodes though, as barebox doesn't
support them anyway.
Link: https://lore.barebox.org/20240205125301.2465254-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The barebox,bootsource-* properties are looked for in /chosen, not in
/aliases. Move the properties to the correct node.
Fixes: 7eedf79ba9 ("ARM: i.MX: add barebox,bootsource-mmc aliases")
Link: https://lore.barebox.org/20240226153117.743128-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|/
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The media_blk_ctrl is hardcoded in the DT to reference a number of power
domains that we delete. The media_blk_ctrl itself is still usable
without them (e.g. LVDS doesn't require ISP), but the probe in Linux
would fail, because the power domain can't be attached.
This has already been fixed once in commit 5600290f4bf1
("/arch/arm/dts: imx8mp: Do not mask out mediamix power domain"), but
got reintroduced recently.
As the upstream DT has no ISP node and we already disable the MIPI DSI
node, let's just leave the power domains untouched and see how that
fares.
Fixes: aaea50bbcde2 ("soc: imx: featctrl: finalize support for i.MX8MP")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240220172527.599962-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Change default_environment_path_set() to take a const char * and let
default_environment_path_get() return a const char *.
Also, do not keep a copy of the string passed to
default_environment_path_set() rather than the original string to make
it more clear where the path is allocated. This allows us to free the
string passed to default_environment_path_set() after usage by some
callers.
Link: https://lore.barebox.org/20240219105507.1618465-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The existing DT was added alongside board support in v2019.05.0.
The board gained an upstream DT in Linux v6.7-rc1, which was pulled
as part of v2023.12.0. So let's drop our copy to avoid duplication.
This change will introduce user noticeable differences:
- barebox compatible, which is also used to match kernel DT, changes
- hostname changes as it's generated from DT compatible
This is deemed acceptable as it aligns us with the upstream DT.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240219133340.3873032-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
CM4S is close to the CM4, and thus is herited from it, with some
minor changes:
* The uart1 node (mini UART) does not need the clock to be forced to
500MHz.
* The compatible field needs to be updated to match the CM4S
There is still an issue with the dwc2 driver in timeout.
Boot log:
Board: Raspberry Pi Compute Module 4S IO Board
deep-probe: supported due to raspberrypi,4-compute-module-s
bcm2835_mci fe300000.mmc@7e300000.of: registered as mci0
WARNING: dwc2 fe980000.usb@7e980000.of: dwc2_core_reset: Timeout! Waiting for Core Soft Reset
ERROR: dwc2 fe980000.usb@7e980000.of: probe failed: Connection timed out
bcm2835_mci fe340000.mmc@7e340000.of: registered as mci1
malloc space: 0x1f17ca80 -> 0x3e2f94ff (size 497.5 MiB)
no /dev/disk0.0 or /dev/mmc0.0. using default env
no '/hat' node found in vc fdt
environment load /dev/env0: No such file or directory
Maybe you have to create the partition.
Hit any to stop autoboot: 3
Signed-off-by: Pierre-Olivier Huard <pierre-olivier.huard@rtone.fr>
Link: https://lore.barebox.org/20240215120109.23242-1-pierre-olivier.huard@rtone.fr
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The BootROM arms the watchdog with the maximum timeout of 16 seconds on
boot. This is ample time to boot into Linux userspace, so so far we
didn't touch the watchdog for the SAMA5D2 in barebox and expected the
user to disable the watchdog manually, e.g. via the `wd -x` command or
by storing nv.autoboot=abort into the environment.
While this works, this is admittedly bad user experience, so let's just
enable watchdog polling in barebox instead. That way, we still have
watchdog supervision, but don't reset when dropping into the barebox
shell.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240212154617.2260448-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Now that we can print MAC addresses using the %pM format specifier we
can get rid of ethaddr_to_string(). Do this treewide.
Link: https://lore.barebox.org/20240202151147.226876-2-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Seems PowerPC in general is missing the IMD sections.
Placement might be suboptimal, please correct if so.
Signed-off-by: Christian Melki <christian.melki@t2data.com>
Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240126075231.1285729-1-christian.melki@t2data.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ \ |
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Several boards overwrite the standard mmc aliases to give them a board
specific numbering. This breaks our assumption that the bootsource
instance number matches the mmc alias numbering. barebox supports
barebox,bootsource-mmc aliases to provide a mapping between the
bootsource and the device nodes that provides them. Add these aliases
for the newer i.MX SoCs.
Link: https://lore.barebox.org/20240220104402.2475000-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
While the underlying architecture of AHAB is quite different than HAB,
the user interface fits into the existing hab command quite well, so
integrate it into the existing HAB infrastructure.
Link: https://lore.barebox.org/20240213151744.307958-7-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
This implements more ELE operations useful for AHAB secure boot.
Link: https://lore.barebox.org/20240213151744.307958-6-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The i.MX9 eMMC boot bbu handler does not work currently, because the
code expects a i.MX image which is not what we need on i.MX9.
The code is also full of i.MX image specific quirks which we don't need
on i.MX9, so use the just created
imx_bbu_internal_mmcboot_register_handler() for i.MX9.
Link: https://lore.barebox.org/20240208075217.697668-2-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
This adds a standard bbu handler to be used when an update is just
a matter of writing an image to the eMMC boot partitions.
As these may also want to set the BBU_FLAG_MMC_BOOT_ACK flag, it is
moved up one level to struct bbu_handler::flags to make it configurable
when struct bbu_data is not yet instantiated.
Link: https://lore.barebox.org/20240208075217.697668-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The LGA variant needs different DDR setup and another device tree. The
board type can be read from EEPROM, so we don't need another image for
it.
Link: https://lore.barebox.org/20240205074553.2005284-9-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The TQ i.MX93 boards come in different variants, all of which can
be identified with an EEPROM. We can support all variants in a single
image, so rename the tqmba9xxxca, which is only one variant, to TQMA93XX
which can be used as a name covering all variants.
Link: https://lore.barebox.org/20240205074553.2005284-8-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The tqma9352-mba93xxca device tree went upstream, so switch to the
upstream version. This is currently nearly identical to our downstream
version, only the PMIC node is not yet in upstream, but we don't need
this for barebox.
Link: https://lore.barebox.org/20240124085146.2308724-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |/ /
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Convert the i.MX8M machine init code to the previously introduced soc
framework. The soc driver was mostly copied from Linux with slightly
adaptions for barebox. To the soc driver is called during the
postcore_initcall to keep the level aligned with the previous imx_init().
The ocotp clock must keept running else the ARM-SMCCC stuck for calls
where the TF-A tries to access the ocotp.
A sample output of the new introduced soc0 device:
|
| barebox@FSL i.MX8MM EVKB:/ devinfo soc0
| Bus: soc
| Parameters:
| family: Freescale i.MX (type: string)
| machine: FSL i.MX8MM EVKB (type: string)
| revision: 1.0 (type: string)
| serial_number: 15182A09DAB5B3C9 (type: string)
| soc_id: i.MX8MM (type: string)
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20240125133856.3792552-2-m.felsch@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |/
|/|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
During bug hunt of a clocking issue that ultimately turned out to be
unrelated, I resynced AT91 clk support with Linux.
The changes look more extensive than they really are, because I first
imported the clock drivers before a major overhaul of the barebox clock
framework to be more compatible with the more recent kernel API changes.
Most of the diff is due to that, but this resync also fixes
at least a USB issue for the at91rm9200 and adds support for
the new SAMA7 SoC as well as more clocks for the SAM9x60. Both these
SoCs aren't supported by barebox yet, but this at least adds clock
driver support.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240215121837.251013-4-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
scratch.c is needed for both i.MX8 and i.MX9, but is compiled only for
i.MX8, so linking will failed if only i.MX9 is enabled.
Add a Kconfig option for it and select it from both i.MX8 and i.MX9.
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20240205125728.2470228-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|/
|
|
|
|
|
|
|
| |
The ELE nvmem support is needed on i.MX9 for reading fuses, especially
for reading MAC addresses from the fuses. Enable it in the relevant
defconfigs.
Link: https://lore.barebox.org/20240131083446.673104-1-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ |
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
All platforms that select COMMON_CLK also select CLKDEV_LOOKUP,
therefore just select it in drivers/clk/Kconfig and drop the
CLKDEV_LOOKUP all over the place.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240118090718.1314156-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
So far, we expected platforms to select COMMON_CLK if they have a clock
controller that's covered by the common clk framework and HAVE_CLK if
they have a legacy clock driver.
With the addition of SCMI clocks, platforms, especially virtualized ones,
that previously didn't need clock support may now want access to them.
Instead of having to select COMMON_CLK from such platforms on the
off-chance that SCMI clocks may need to be used, just make COMMON_CLK
user visible, so it can be selected as needed. As COMMON_CLK needs to
conflict with legacy clock support, we also add a symbol for that and
start selecting it where appropriate,
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240118090718.1314156-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
<dma.h> will take care to define dma_alloc with DMA_ALIGNMENT as
alignment. As 32 is the default and may not be applicable to the used
processor, we define DMA_ALIGNMENT and drop the now duplicate code.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240108102438.1318473-3-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
<dma.h> will take care to define dma_alloc with DMA_ALIGNMENT as
alignment. As 32 is the default and we for need 64 for kvx,
define DMA_ALIGNMENT and drop the now duplicate code.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Yann Sionneau <ysionneau@kalrayinc.com>
Link: https://lore.barebox.org/20240108102438.1318473-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
<dma.h> will take care to define dma_alloc with DMA_ALIGNMENT as
alignment. As 32 is the default and we for some reason, use 64 for
sandbox, define DMA_ALIGNMENT and drop the now duplicate code.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240108102438.1318473-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Thanks to Denis Orlov's work on dma_sync_single_for_*()
interface and e1000 patches we can enable e1000 support
on both 32-bit and 64-bit qemu malta boards.
32-bit malta qemu command line:
qemu-system-mips -M malta -cpu 24Kf -m 256M \
-nographic -serial mon:stdio \
-bios images/barebox-qemu-malta.img \
-net user,tftp=$(pwd) -net nic,model=e1000
64-bit malta qemu command line:
qemu-system-mips64el -M malta -cpu MIPS64R2-generic -m 256M \
-nographic -serial mon:stdio \
-bios images/barebox-qemu-malta.img.swapped \
-net user,tftp=$(pwd) -net nic,model=e1000
Barebox commands to check e1000 network interface:
barebox@qemu malta:/ devinfo eth0
Parent: pci-8086:100e.0
Parameters:
ethaddr: 52:54:00:12:34:56 (type: MAC)
gateway: 0.0.0.0 (type: ipv4)
ipaddr: 0.0.0.0 (type: ipv4)
linux.bootargs: (type: string)
linux.devname: (type: string)
mode: dhcp (type: enum) (values: "dhcp", "static", "disabled")
netmask: 0.0.0.0 (type: ipv4)
serverip: (type: string)
barebox@qemu malta:/ devinfo pci-8086:100e.0
Driver: e1000
Bus: pci
Parameters:
class: 0200 (type: string)
devfn: 90 (type: string)
device: 100e (type: string)
revision: 0003 (type: string)
vendor: 8086 (type: string)
barebox@qemu malta:/ dhcp eth0
eth0: DHCP client bound to address 10.0.2.15
barebox@qemu malta:/ tftp images/barebox-qemu-malta.img
[################################################################]
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Link: https://lore.barebox.org/20240103105246.800751-1-antonynpavlov@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
pmic_reg_write() does 8 bit writes, so rename the function accordingly.
When adding 16/32 bit writes there is no point in abstracting the
register width in pmic_reg_write(), because the caller actually must
know the register width to make useful register changes. This means
we better add pmic_reg_write16/32 when need arises.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
| |
| |
| |
| |
| |
| | |
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Link: https://lore.barebox.org/20240101112359.721688-1-antonynpavlov@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|\ \ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The SCFG_SNPCNFGCR USB bits only have an effect if the
Layerscape-specific bits in each DWC instance's GSBUSCFG0 are
appropriately configured.
As the LS1046's kernel DT is configured to assume the whole SoC is dma-coherent,
we need to set these bits, so this is indeed the case.
This configuration is likewise applicable to the LS1043A, should
we add support for it and to the newly added LS1028A, if we start
configuring the CCI-400 to make the fully cache-coherent, but alas,
that's not yet the case and the LS1028A's kernel DT doesn't assume it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20240110160112.4134162-12-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|