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* ARM: mmu: align size of remapped region to page sizeHEADmasterAhmad Fatoum44 hours2-0/+6
| | | | | | | | | | | | | | | | Currently, barebox ARM arch_remap_range() will hang in an infinite loop, when called with a size that's not aligned to a page boundary. Its Linux equivalent, ioremap(), will just rounds up to page size and work correctly. Adopt the Linux behavior to make porting code easier, e.g. when calling devm_ioremap(). The only other arch_remap_range() in barebox, is PowerPC's. That one wouldn't loop indefinitely if the size isn't page aligned, so nothing to do there. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231205081247.4148947-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: dts: i.MX8MP: imx8mp-skov: fix reserved-memory cellsAhmad Fatoum44 hours1-2/+2
| | | | | | | | | | | | | | Build complains about: imx8mp-skov.dts:69.3-10: Warning (ranges_format): /reserved-memory:ranges: empty "ranges" property but its #size-cells (1) differs from / (2) (48 results) [482/38498] Fix this by changing the cell size to what's in imx8mp.dtsi's /. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231204164938.1130386-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Rockchip: dmc: print memory sizes in hexSascha Hauer3 days1-1/+1
| | | | | | | | Large decimal numbers are not readable and useful, print memory sizes in hexadecimal instead. Link: https://lore.barebox.org/20231201151044.1648393-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM64: mmu: panic when out of PTEsSascha Hauer3 days1-0/+3
| | | | | | | | When running out of PTEs panic with an appropriate message instead of continuing with NULL pointers. Link: https://lore.barebox.org/20231201151044.1648393-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM64: mmu: Fix alloc_pte() address calculationSascha Hauer3 days1-1/+1
| | | | | | | | | | | | | | | get_ttb() returns an uint64_t * which means that with get_ttb() + idx * GRANULE_SIZE the distance between two PTEs is wrongly calculated as 0x8000 bytes instead of 0x1000 bytes. With this we leave the space allocated for PTEs quite fast and the available space check also doesn't work. Fix this by explicitly casting to void *. Link: https://lore.barebox.org/20231201151044.1648393-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32mp1'Sascha Hauer10 days4-90/+27
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| * ARM: stm32mp: stm32mp15x-ev1: enable deep probeAhmad Fatoum14 days1-1/+2
| | | | | | | | | | | | | | | | | | The board boots fine with deep probe enabled, so enable it to eliminate probe deferrals. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122181319.706228-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: init: ignore of_register_fixup return valueAhmad Fatoum14 days1-8/+3
| | | | | | | | | | | | | | | | | | of_register_fixup can't actually fail, so drop the return value check and propagation to make the code a bit more concise. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122181116.591131-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: init: don't print STM32MP15 CPU typeAhmad Fatoum14 days1-43/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TF-A already reads the OTP and unconditionally prints at a higher log level: NOTICE: CPU: STM32MP157AAA Rev.B barebox reads the OTP again via the secure monitor only to print: stm32mp-init: detected STM32MP157AAA Rev.B which doesn't add any extra information, so drop it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122181116.591131-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: init: handle differences between STM32MP13 and STM32MP15Ahmad Fatoum14 days2-33/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | setup_cpu_type() was responsible for registering fixups for STM32MP15 and for initializing the values returned by stm32mp_silicon_revision(), stm32mp_cputype() and stm32mp_package(). It has no support for STM32MP13 and the OTP on that SoC is accessed differently from the STM32MP15, so let's just mark the function STM32MP15-specific and delete all helpers that have no users instead of having to duplicate them for STM32MP13. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122181116.591131-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: stm32mp: init: drop unused macrosAhmad Fatoum14 days1-4/+0
| | | | | | | | | | | | | | | | | | | | The use of the TAMP registers differs between STM32MP15 and STM32MP13, so let's drop all register definitions that we don't use instead of renaming them to be SoC-specific. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122181116.591131-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: dts: stm32mp: fix model string for stm32mp135f-dkAhmad Fatoum14 days1-1/+1
| | | | | | | | | | | | | | | | STM32MP153 is another SoC. Fix the typo. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122181116.591131-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: dts: stm32mp: stm32mp135-dk: drop duplicate propertyAhmad Fatoum14 days1-4/+0
| | | | | | | | | | | | | | | | | | The upstream device tree being included already has the same /chosen/stdout-path, so drop it from the barebox DT. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122181116.591131-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/prepare-optee'Sascha Hauer10 days11-2/+355
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| * | include: import Linux word-at-a-time.hAhmad Fatoum14 days9-0/+353
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux <linux/word-at-a-time.h> interface is used to optimize searching for bytes in strings by doing word-size comparisons. This will be used in the implementation of strscpy in a follow-up commit, so import the generic version here. A good overview on the interface is available at LWN[1]. Note that it discuss Linux v3.5. The asm-generic version imported here works also on little-endian and not only big-endian[2]. [1]: https://lwn.net/Articles/501492/ [2]: Linux kernel commit a6e2f029ae34 ("Make asm/word-at-a-time.h available on all architectures"). Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122172951.376531-9-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | include: provide linux/errno.hAhmad Fatoum14 days2-2/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't have the historic baggage of having to support different errno definitions depending on architecture. We thus have only asm-generic/errno.h and include that from errno.h and elsewhere directly. Kernel code however includes <linux/errno.h>, so let's provide that file as well and define there the Linux-specific errno's and include <asm-generic/errno.h> for all other errnos. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122172951.376531-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer10 days10-11/+46
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| * | MIPS: qemu-malta*_defconfig: enable virtio network driverAntony Pavlov10 days2-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20231124060130.1205927-3-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | sandbox: libc_malloc: populate barebox errno on errorAhmad Fatoum14 days1-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | TLSF already populates errno on errors, so do likewise for the allocators that don't. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231122170007.3849506-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: ls1046a: use compressed dtbsSascha Hauer2023-11-213-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | It's getting tight in the initial 64k SRAM space. Use compressed dtbs to get some more free space. Link: https://lore.barebox.org/20231120133930.3946286-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | console: move ARCH_HAS_CTRLC into KconfigAhmad Fatoum2023-11-213-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should do away altogether with <asm/common.h>, so prepare for doing that in the future by moing the only content it has on sandbox into Kconfig. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231109124326.1499612-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: stm32mp: fix typo in STM32MP135-DK promptAhmad Fatoum2023-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board is called STM32MP135 and there is currently no STM32MP137. The typo was likely caused by copy-pasting from the STM32MP15x, which has STM32MP157. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231109130253.1506400-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/k3'Sascha Hauer10 days13-0/+154
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| * | | ARM: multi_v8_defconfig: Enable K3 SoCsSascha Hauer2023-11-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enabled everything necessary for running barebox on K3 SoCs Link: https://lore.barebox.org/20230803105003.4088205-23-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: k3: BeaglePlay: Work around non working SD cardSascha Hauer2023-11-061-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The upstream dts file configures the SD card detect pin as GPIO. With this our SD driver currently doesn't work. Until the reasons are found out let's configure the pin as native card detect for now. Link: https://lore.barebox.org/20230803105003.4088205-20-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: k3: Add initial BeaglePlay board supportSascha Hauer2023-11-067-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic 2nd stage support for the BeaglePlay board, see https://docs.beagle.cc/latest/boards/beagleplay/index.html The BeaglePlay is based on the Texas Instruments AM62x (K3) SoC. 1st stage support is out of scope for now, but current support is enough to be started as a Kernel from running U-Boot using the booti command. When encapsulated in a FIT image the resulting image can replace u-boot.img to directly boot into barebox. Link: https://lore.barebox.org/20230803105003.4088205-19-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: Add Texas Instruments K3 architectureSascha Hauer2023-11-065-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the Kconfig snippets for supporting the Texas Instruments K3 architecure. This also enables deep probe support on a SoC basis as all new boards should work with deep probe enabled. Likewise we need PM domain support for the initially supported AM62x SoC, so enable that for this SoC as well. Link: https://lore.barebox.org/20230803105003.4088205-18-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM64: Add support for debug_ll on TI AM62x SoCsSascha Hauer2023-11-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI K3 SoCs have ns16550 compatible UARTs. Add lowlevel debugging support for the AM62x SoC from the K3 family. Link: https://lore.barebox.org/20230803105003.4088205-5-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | Merge branch 'for-next/imx'Sascha Hauer10 days29-162/+3914
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| * | | | ARM: multi_v8_defconfig: enable i.MX9 boardsSascha Hauer2023-11-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Link: https://lore.barebox.org/20231110125800.1901232-26-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Update imx_v8_defconfigSascha Hauer2023-11-201-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable i.MX9 support and drivers useful on that SoC. Link: https://lore.barebox.org/20231110125800.1901232-25-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Add TQ MBA9XXXCA board supportSascha Hauer2023-11-208-0/+2420
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TQ MBA9XXXCA is a i.MX93 based board, see https://www.tq-group.com/de/produkte/tq-embedded/arm-architektur/stka93xx/ Link: https://lore.barebox.org/20231110125800.1901232-17-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: atf: add imx93_load_and_start_image_via_tfa()Sascha Hauer2023-11-201-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | Link: https://lore.barebox.org/20231110125800.1901232-21-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: romapi: Implement i.MX93 supportSascha Hauer2023-11-201-4/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We used to use the ROM API for USB loading only, now with i.MX93 we fully rely on the ROM API also with SD/eMMC and other boot sources. The ROM provides us information about the boot source. There are generally two types of boot sources: seekable for storage devices like SD/eMMC and streamable for USB. the load_image call must be handled slightly different for both types of boot sources, so we fist detect which type we have and call the right load_image function accordingly. Link: https://lore.barebox.org/20231110125800.1901232-20-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: romapi: rename functions to *romapi*Sascha Hauer2023-11-202-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The file the romapi is implemented in is named romapi and that's also the name the i.MX ROM API is normally referred to, so rename the functions accordingly. While at it, rename some internal functions from imx8m_* to imx_* as they can and will also be used by upcoming i.MX9 support. Link: https://lore.barebox.org/20231110125800.1901232-19-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX93: Add DDR size read supportSascha Hauer2023-11-201-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | Link: https://lore.barebox.org/20231110125800.1901232-18-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: Add local imx93.dtsiSascha Hauer2023-11-201-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current upstream i.MX93 dtsi lacks some nodes currently, add them locally until merged upstream: - add USB nodes - add DDRC node - add OCOTP ethernet MAC address nodes Link: https://lore.barebox.org/20231110125800.1901232-14-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: initial i.MX9 supportSascha Hauer2023-11-206-2/+249
| | | | | | | | | | | | | | | | | | | | | | | | | Link: https://lore.barebox.org/20231110125800.1901232-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: Add i.MX93 TRDC supportSascha Hauer2023-11-202-0/+318
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to initialize the Trusted Resource Domain Controller (TRDC). This is needed very early in PBL to reconfigure the OCRAM read/write. Without this initialization OCRAM is readonly and relocate_to_current_adr() won't work. The code is taken from U-Boot as of 2023.10-rc4. Link: https://lore.barebox.org/20231110125800.1901232-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX: Add ELE communication supportSascha Hauer2023-11-202-0/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We'll have to communicate to the EdgeLock Secure Enclave in a followup patch. Add support for that. Code is taken from U-Boot as of 2023.10-rc4. Link: https://lore.barebox.org/20231110125800.1901232-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | usb: gadget: i.MX: Move PBL USB gadget driver to arch/Sascha Hauer2023-11-133-0/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX PBL USB gadget driver is currently selected by architecture Kconfig options. When USB gadget support is disabled then the build system doesn't descend into the directory where the driver is, leading to undefined references. We could change that and descend into the directory unconditionally, but as the driver doesn't have any dependencies to the USB gadget framework we can also move the driver to arch/arm/mach-imx/ to solve this problem. Link: https://lore.barebox.org/20231110130246.2222936-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ddr: imx8m: get rid of hardcoded phy addressSascha Hauer2023-11-133-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phy address is hardcoded in several functions. Use the address provided in struct dram_controller instead. Some functions are used from legacy DDR setup in board code which only uses parts of the DDR initialization code. The board code doesn't have any struct dram_controller *, so provide some static inline wrappers for these functions. Link: https://lore.barebox.org/20231110130028.2123895-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX8M: detangle lowlevel codeSascha Hauer2023-11-131-36/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX8M lowlevel code uses some macros which take SoC prefix names as arguments which then expand to SoC specific function names. The result is hard to follow. Detangle this by open coding the macros. At the expense of a bit of code duplication we gain readability. Link: https://lore.barebox.org/20231110094622.877614-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | ARM: i.MX8MQ: Streamline lowlevel startup codeSascha Hauer2023-11-135-99/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most i.MX8M SoCs have a imx8m[nmp]_load_and_start_image_via_tfa() function which does all the magic of loading and starting TF-A, barebox proper and OP-TEE images. Only the i.MX8MQ boards have the same open coded in the lowlevel code. Implement a imx8mq_load_and_start_image_via_tfa() and switch the i.MX8MQ boards over to it. Link: https://lore.barebox.org/20231110094622.877614-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | Merge branch 'for-next/dts'Sascha Hauer10 days1-54/+0
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| * | | | | dts: update to v6.7-rc1Sascha Hauer2023-11-161-54/+0
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* | | | | ARM: layerscape: ppa: Enable MMU when in EL2Sascha Hauer10 days1-0/+7
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | We enter EL2 with MMU disabled even when it was enabled in EL3. Enable MMU in EL2 again. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | ARM: layerscape: ppa: Fix starting PPASascha Hauer2023-11-211-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With dba1c26f70 we replaced request_sdram_region() for the PPA with reserve_sdram_region(). The effect is that the region is marked as reserved and mapped non executable. While this is desired for EL2, it also has the effect that we can't start the PPA anymore from EL3. Map the region cached/executable to start the PPA, then map it uncached/non executable once we are in EL2. Fixes: dba1c26f70 ("arm: layerscape: ppa: reserve SDRAM region for PPA") Link: https://lore.barebox.org/20231120144453.1075740-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | ARM: mmu64: setup ttb for EL2 as wellSascha Hauer2023-11-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TF-A is often started before the MMU is initialized. There are some exceptions though. On Layerscape the TF-A (or: PPA in that case) is started while the MMU is running. The PPA is then executed in EL3 and returns in EL2. For this case setup the TTB for EL2 as well so that we have a valid MMU setup when the PPA returns. Link: https://lore.barebox.org/20231120144453.1075740-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | ARM: arria10: xload: retry FPGA configurationBruno Knittel2023-11-211-12/+37
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel documentation states that the FPGA configuration might fail. This has been observed on the Enclustra AA1+ board where up to 4 retries where required to configure the FPGA. Debugging session showed that the data where correctly read from the eMMC but yet the configuration failed. This commit introduces a retry loop on the FPGA configuration. Up to 10 retries (arbitrary) are attempted. As the hardware can't be used anyway without the FPGA loaded, this doesn't introduce any boot time problems. Taking longer is better than just hang()ing. Signed-off-by: Bruno Knittel <bruno.knittel@bruker.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20231115-arria10-fpga-reload-on-failure-v2-1-6a45f125c9c2@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.1 (git 2.18.0) at 2023-12-07 03:56:45 +0000