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* ARM64: let 'end' point after the range in cache functionsEnrico Scholz7 days2-3/+3
| | | | | | | | | | | | | | | v8_flush_dcache_range() and v8_inv_dcache_range() are implemented under the assumption that their 'end' parameter points *after* the range. Fix callers to use it in this way. This fixes e.g. spurious corruptions in the last octet when sending 129 bytes over ethernet. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Link: https://lore.barebox.org/20240412162836.284671-1-enrico.scholz@sigma-chemnitz.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* RISC-V: riscvemu: build overlay as DTSOAhmad Fatoum2024-04-033-3/+3
| | | | | | | | | | Overlay files shouldn't include the device tree snippets from CONFIG_EXTERNAL_DTS_FRAGMENTS, which is avoided by using the dtbo rule instead of the dtb rule that we were using before. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240402134501.3689322-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* zynqmp: firmware: add functions to set tap delaySteffen Trumtrar2024-03-181-0/+42
| | | | | | | | Add a function to set the tap delay for the clk phase of the sd host controller. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* ARM: zynqmp: add sd_dll_reset callSteffen Trumtrar2024-03-181-0/+17
| | | | | | | Add a function to reset DLL logic for SD devices. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2024-03-155-2/+62
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| * MIPS: add generic device tree 2nd stage supportAntony Pavlov2024-03-135-2/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building and running barebox for 32-bit malta: export ARCH=mips export CROSS_COMPILE=mips-linux-gnu- make -s qemu-malta_defconfig sed -i "s/# \(CONFIG_BOARD_MIPS_GENERIC_DT\) is not set/\1=y/" .config make -s oldconfig make -s qemu-system-mips -M malta -cpu 24Kf -m 256M \ -nographic -serial mon:stdio \ -bios images/barebox-qemu-malta.img \ -net user,tftp=$(pwd) -net nic,model=e1000 Building and running barebox for 64-bit malta: export ARCH=mips export CROSS_COMPILE=mips-linux-gnu- make -s qemu-malta64el_defconfig sed -i "s/# \(CONFIG_BOARD_MIPS_GENERIC_DT\) is not set/\1=y/" .config make -s oldconfig make -s qemu-system-mips64el -M malta -cpu MIPS64R2-generic -m 256M \ -nographic -serial mon:stdio \ -bios images/barebox-qemu-malta.img.swapped \ -net user,tftp=$(pwd) -net nic,model=e1000 Use bootm to run barebox-dt-2nd.img (external device tree): barebox@qemu malta:/ dhcp barebox@qemu malta:/ cp /mnt/tftp/images/barebox-dt-2nd.img barebox.img barebox@qemu malta:/ cp /mnt/tftp/arch/mips/dts/qemu-malta.dtb . barebox@qemu malta:/ imd barebox.img barebox@qemu malta:/ bootm -o qemu-malta.dtb barebox.img Use bootm to run barebox-qemu-malta.img (encapsulated device tree): barebox@qemu malta:/ dhcp barebox@qemu malta:/ cp /mnt/tftp/images/barebox-qemu-malta.img barebox.img barebox@qemu malta:/ imd barebox.img barebox@qemu malta:/ bootm barebox.img N.B. Use just the same commands for both 32-bit and 64-bit malta boards. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Link: https://lore.barebox.org/20240310215434.1220451-1-antonynpavlov@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2024-03-1555-1337/+5564
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| * | arm: imx8mp: add karo electronics qsxp-ml81 som supportMarc Kleine-Budde2024-03-1311-0/+1044
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ka-Ro QSXP is a i.MX8M Plus solder down system on module. This commit adds support for the SOM on the QSBASE4 RDK. [1]: https://www.karo-electronics.de/qsxp Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Link: https://lore.barebox.org/20240311-karo-imx8mp-som-board-upstreaming-v2-6-6ecda693adb2@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | arm: dts: karo: add karo imx8mp-karo-qsxp-ml81-qsbase4Stefan Kerkmann2024-03-131-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ka-Ro QSXP-QSBASE4[1] is the offical DK from Ka-Ro for their QSXP i.MX8M Plus solder down system on module. It comes with an additional Micrel KSZ9131 gigabit ethernet phy. The devicetree was adapted from the offical Ka-Ro github[2], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6. [1]: https://karo-electronics.github.io/docs/getting-started/qsbase4/quickstart-qsbase4.html [2]: https://github.com/karo-electronics/meta-karo-nxp.git Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Link: https://lore.barebox.org/20240311-karo-imx8mp-som-board-upstreaming-v2-5-6ecda693adb2@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | arm: dts: karo: import dts for karo-qsxp-ml81Marc Kleine-Budde2024-03-133-0/+581
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This imports the device tree for the Ka-Ro QSXP, which is a i.MX8M Plus solder down system on module. The sources have been adapted from the offical Ka-Ro github[1], commit a49b38ec97854c0cd9cd83a9f4ae3b56e99a58b6. [1]: https://github.com/karo-electronics/meta-karo-nxp.git Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Link: https://lore.barebox.org/20240311-karo-imx8mp-som-board-upstreaming-v2-4-6ecda693adb2@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: ele: add ele_write_shadow_fuseSascha Hauer2024-03-131-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ocotp fuses have shadow values. For some fuses the shadow values can be read from and written to. While it's not really clear where the ROM really uses these shadow values, it still helps reading and writing them to get an idea if we are about to write the correct fuses before we finally enable permanent write. Link: https://lore.barebox.org/20240311102152.360762-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: ele: add function commentsSascha Hauer2024-03-131-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX fuse numbers are sometimes referred to as the index of the 32bit word, sometimes as bit offsets and the device in /dev/imx_ocotp counts in bytes. To avoid more confusion add some comments to the function headers of functions reading/writing the fuses that clearly state that they take the 32bit word number as input. Link: https://lore.barebox.org/20240311102152.360762-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: ele: move ELE_READ_SHADOW_REQ definitionSascha Hauer2024-03-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | The ELE request defines are in include/mach/imx/ele.h, move definition of ELE_READ_SHADOW_REQ there as well. Link: https://lore.barebox.org/20240311102152.360762-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8MP: add König+Bauer AlphaJet boardJohannes Zink2024-03-1314-0/+3307
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for König+Bauer AlphaJet, based on a Congatec QMX8MP SoM with an i.MX8MP SoC in the Industrial Temperature Grade 4GB Variant, no inline ECC used. Co-Developed-by: Juergen Borleis <j.borleis@pengutronix.de> Signed-off-by: Juergen Borleis <j.borleis@pengutronix.de> Signed-off-by: Johannes Zink <j.zink@pengutronix.de> Signed-off-by: Roland Hieber <rhi@pengutronix.de> Link: https://lore.barebox.org/20240311140455.3094462-1-rhi@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | imx25: Feed the unique id to machine_id_set_hashable()Uwe Kleine-König2024-03-131-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | This enables barebox on i.MX25 to generate a per-machine eth address. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.barebox.org/20240312154827.638763-2-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8MP: skov: add MAC address assignment supportOleksij Rempel2024-03-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Assign MAC address to the switch ports. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.barebox.org/20240312142708.3766405-1-o.rempel@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: ele: remove unnecessary argumentSascha Hauer2024-03-131-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | The get_response argument to imx9_s3mua_call() is always set to true by the callers. It must be like that because in the ELE API Reference Guide every call into the ELE has a response. Drop the unnecessary argument. Link: https://lore.barebox.org/20240301111915.2439646-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: sabresd: Add support for i.MX6DL board variantStefano Manni2024-03-135-3/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SabreSD comes with different SoC variants. This patch adds support for the i.MX6DL based board. the DCD data has been taken from U-Boot 2023.04 Signed-off-by: Stefano Manni <stefano.manni@gmail.com> Link: https://lore.barebox.org/4b448318f71f2677bc28c2241c5bf0c081073564.camel@gmail.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | arm: mach-imx: tzasc: convert to cpu_is_mx8xyz macrosStefan Kerkmann2024-03-132-24/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing in configuration parameters at runtime we can utilize the `cpu_is_mx8xyz` macro family to determine which bits should be set. As the tzasc driver is imx specific, all functions are prefixed with `imx8m_` as well. Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Link: https://lore.barebox.org/20240228-v2024-02-0-topic-imx8m-n-p-tzac-v2-3-ee1ae48dc399@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | arm: mach-imx: set cpu type in pblStefan Kerkmann2024-03-132-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to use the `cpu_is_imxxyz` macro family in the pbl, `__imx_cpu_type` has to be defined and initialized. As we don't have access to the devicetree at this point, we resort to manual assignment. Note: It is safe to build the same imx.o object file for both barebox pbl and proper as the `imx_init` function is discarded during linking as the whole `init_call` section is not linked into the final binary. Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Link: https://lore.barebox.org/20240228-v2024-02-0-topic-imx8m-n-p-tzac-v2-2-ee1ae48dc399@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | arm: mach-imx: tzasc: lock id_swap_bypass bitStefan Kerkmann2024-03-131-10/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit ports U-Boot commit 1289ff7bd7e4 ("imx8m: lock id_swap_bypass bit in tzc380 enable") to barebox. This is the original commit message: > According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock > bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in > order to avoid AXI bus errors when GPU is enabled on the platform. > TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable > derivatives, but is missing a lock settings to be applied. > > Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have > it implemented. > > Since we're here, provide also names to bits from TRM instead of using > BIT() macro in the code. Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de> Link: https://lore.barebox.org/20240228-v2024-02-0-topic-imx8m-n-p-tzac-v2-1-ee1ae48dc399@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX93: add bootsource detectionSascha Hauer2024-03-132-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | On i.MX93 the ROM API can be used to detect the bootsource. Implement support for this. Link: https://lore.barebox.org/20240220114508.3685478-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX6ul: TQMa6ul: install barebox on eMMC boot partitionsSascha Hauer2024-03-132-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | Install barebox on the eMMC boot partitions which offer enough space for bigger barebox images and which also provides a failsafe update. Link: https://lore.barebox.org/20240226141458.620463-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX6ul: TQMa6ul: fix mmc aliasesSascha Hauer2024-03-133-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TQMa6ul upstream device trees contain aliases which swap the order of the mmc nodes, so what used to be mmc0 has now become mmc1 and vice versa. With this mmc0 now is the eMMC and mmc1 is the SD card. Introduce a imx6ul.dtsi which adds barebox,bootsource-mmcx aliases so that bootsource_get_instance() matches our mmc numbering again. Also register the eMMC BBU handler on /dev/mmc0 and the SD BBU handler on /dev/mmc1. Fixes: 5a23f05267 ("ARM: tqma6ul: use upstream device trees") Link: https://lore.barebox.org/20240226141458.620463-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX6: TQMa6ulx: add OP-TEE supportSascha Hauer2024-03-134-11/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds OP-TEE support for the TQMa6ulx board. The OP-TEE binary is loaded from PBL. Later on in barebox proper the OP-TEE provided overlay node is applied to the barebox live tree for barebox to probe OP-TEE and also to reserve the memory used by OP-TEE. The overlay is also registered as a fixup to be applied on the Linux device tree. Link: https://lore.barebox.org/20240223125922.2865359-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX8MM: innocomm-wb15: switch to upstream DTAhmad Fatoum2024-03-133-629/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same DTs we have in barebox have made it upstream with very minor differences, so drop the copies inside barebox. No functional change intended. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220123215.3758465-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: i.MX: phytec-som-imx6: use strdup instead of basprintfAhmad Fatoum2024-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using basprintf to duplicate a string violates memory safety if default_environment_path were to contain a format specifier. clangd warns about this, so fix this by using strdup instead. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220122004.3725540-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: tqma6ul: use upstream device treesSascha Hauer2024-03-1313-641/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tqma6ul has several upstream device trees depending on the exact board type. This removes the downstream device tree in favour for the upstream device trees. The board type can be determined from an EEPROM on the board. This patch also adds support for reading the EEPROM and picking the right device tree for the board found. The EEPROM has the board described as strings. I do not know the correct strings for the boards I don't have, so right now only the device tree for the "TQMa6UL2L-AB.0202" board is picked. A warning is printed when an unknown board type is found, so this can be added as new board type when found. Link: https://lore.barebox.org/20240221150323.2715164-9-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: tqma6ul: enable enet_ref_125m clkSascha Hauer2024-03-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The TQMa6ul needs the enet_ref_125m clk as phy clock. This is currently not enabled, so ethernet on fec2 is not working. As there's no good place to enable it currently do this in the board code. Link: https://lore.barebox.org/20240221150323.2715164-7-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: tqma6ul: add pr_fmt stringSascha Hauer2024-03-132-0/+2
| | | | | | | | | | | | | | | Link: https://lore.barebox.org/20240221150323.2715164-6-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | board: tq: add support for 16bit eepromSascha Hauer2024-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some I2C EEPROMs must be addressed with two bytes. Add the address argument to pbl_tq_read_eeprom(). The actual EEPROM address will be 0x0 always, but we can use the address to pass I2C_ADDR_16_BIT through it. Link: https://lore.barebox.org/20240221150323.2715164-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/hwrng'Sascha Hauer2024-03-153-13/+67
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| * | | hw_random: add OMAP RNG driverAhmad Fatoum2024-03-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable proper hardening with stack protector, add support for the OMAP RNG driver. This has been tested on a Beagle Bone Black. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313105631.686778-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | hw_random: add Rockchip RNG supportAhmad Fatoum2024-03-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable proper hardening with stack protector, add support for the Rockchip RNG. This has been tested on the RK3568. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313105631.686778-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: io: read 32 bits at once for aligned I/O memcpy/memsetAhmad Fatoum2024-03-151-13/+54
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The barebox arm32 implementation for I/O memcpy/memset uses single byte accesses exclusively. This is different from the barebox arm64 implementation, which accesses 64 bits at once if the buffer is aligned and the Linux arm32 implementation, which is the optimized assembly version that doesn't use single byte accesses for aligned buffers either. The current implementation is slower than need be and breaks code ported from Linux. e.g. the OMAP RNG driver uses memcpy_fromio and expects it to perform 32-bit accesses as any smaller access leads to a data abort on the hardware. In Linux this works, but in barebox it crashes. Avoid these issues by using 32-bit accesses if possible. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313105631.686778-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/at91'Sascha Hauer2024-03-159-164/+191
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| * | | ARM: AT91: skov-arm9cpu: support environment on SD-CardAhmad Fatoum2024-02-232-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox is meant to boot from SD-Card on this platform, so support a barebox environment in this case for easier handling. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-15-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: skov-arm9cpu: configure more appropriate hostnameAhmad Fatoum2024-02-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default logic would set the hostname to arm9-cpu, which isn't very descriptive. Set our own hostname that contains the vendor name. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-14-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: skov-arm9cpu: configure SMC for NOR flash useAhmad Fatoum2024-02-231-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deployed ARM9CPU's boots from NOR, not NAND. Replace the EBI NAND configuration taken from the EK with one appropriate for the NOR chip we have. As this needs to happen earlier than the cfi-flash driver probe, we also move the board code to coredevice initlevel. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-13-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: skov-arm9cpu: Add SD-Card xload supportSam Ravnborg2024-02-232-105/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This updates skov-arm9cpu with xload support, and we can now use barebox as a replacement for at91bootstrap Only boot via SD card is supported. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: dts: AT91: skov-arm9cpu: remove barebox environment on NORAhmad Fatoum2024-02-231-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NOR-Flash for ARM9CPUs in the field has U-Boot, so it's not a good idea to overwrite its environment with barebox'. We'll add a SD-Card environment for barebox in recovery case in a later commit, but for now remove the NOR flash environment footgun. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-11-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: sam9263_ll: support configuration of PLLBAhmad Fatoum2024-02-232-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLLB may be used as input to derive the USB's 48 MHz clock. PLLA is already being setup by currently unused sam9263_lowlevel_init(), so add an extra parameter for PLLB as well. While at it, we change the API of sam9263_lowlevel_init(): AT91Bootstrap code has PLLA_SETTINGS and PLLB_SETTINGS as hex values in the headers, so it makes porting easier by just allowing low-level barebox code to use the values as is without having to split them up to stuff into a struct, only to have them ORed into a single value again. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-10-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: sam9263_ll: refactor MCK switch to PLLA for clarityAhmad Fatoum2024-02-231-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Duplicating the bits being written to configure the MCK harms readability, so factor that out into a new variable to make clear the bits that change between the two calls to at91_pmc_cfg_mck(). Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-9-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: sam9263_ll: pass AT91_PMC_LL_AT91SAM9263 to PMC functionsAhmad Fatoum2024-02-231-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The low level PMC driver does things differently according to its flags parameter that encodes what SoC is being used. The default case of flags == 0 is appropriate for the AT91SAM9263, but we have a AT91_PMC_LL_AT91SAM9263 macro that expands to 0, which makes apparent that we take the necessary precautions, so use that instead for documentation purposes. No functional change. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: sam9263_ll: drop PLL charge pump initializationAhmad Fatoum2024-02-231-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The datasheet[1] described the PLL Charge Pump Current Register in 27.9.17 very sparingly by mandating that 0x10001 is to be written into it. In the 28-Jan-16 revision of the datasheet the access mode for the register was changed from Write-only to Read/Write. Indeed reading the register is possible, but it seems to always return 0, even directly after write. Given that code for initializing the PLL charge pumps was added to AT91Bootsrap only for SAMA5 support and that apparently no adverse effect was observed on SAM9263 for not doing this for all these years, it follows that the PLL charge pump has to be already initialized on POR or by BootROM and we are better off playing it safe and not introducing code in the PMC setup that didn't exist in Atmel's own AT91Bootstrap. Therefore drop that line again. There are no upstream boards calling this function yet anyway, so this should have very limited effect. [1]: Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16 Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: at91: use AT91 header instead of generic barebox ARM'sAhmad Fatoum2024-02-233-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to the multi-arch (really multi-platform) rework, ENTRY_FUNCTION used to be overrideable according to selected machine/SoC family. Now that there is no single selected family, board code needs to be explicit in choosing the SoC-appropriate ENTRY_FUNCTION. This was done for nearly all AT91 boards in-tree, but three were missed, which is what's fixed here. This breakage likewise affects all out-of-tree boards, which will misbehave after an update to a newer barebox when used as first stage. Fixing that might be more effort though, so let's just fix what we got in-tree. Fixes: 4331e488f363 ("ARM: at91: Use ENTRY_FUNCTION_HEAD") Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM: replace ENTRY_FUNCTION_HEAD with ENTRY_FUNCTION_WITHSTACK_HEADAhmad Fatoum2024-02-231-6/+14
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow SoC-specific entry functions that don't replicate the code in ENTRY_FUNCTION, we provide a helper macro that support specifying a custom HEAD, but only on arm32. Make this macro private by prefixing with __ and implement the superset ENTRY_FUNCTION_WITHSTACK_HEAD for both arm32 and arm64 that should be used instead. Eventually, we will want to switch away from naked functions on arm32, like we did on arm64 and then we could use the same implementation for both platforms (and support clang on arm32!), but till then, this seems the least ugly way to go about it. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240220093100.1539120-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/arm-efi-prepare'Sascha Hauer2024-03-1524-55/+285
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| * | | commands: add cpuinfo -s option for stacktraceAhmad Fatoum2024-03-051-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While a call to dump_stack() is easily hacked into the code, it can be useful during development to just print the stacktrace from the shell, e.g. to verify that kallsyms sharing for EFI works as intended. Add an option to cpuinfo to provide this functionality. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240304190038.3486881-98-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | ARM64: add optional EFI stubAhmad Fatoum2024-03-0514-10/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While very recent binutils releases have dedicated efi-*-aarch targets, we may want to support older toolchains. For this reason, we import the kernel's EFI stub PE fakery, so the same barebox-dt-2nd.img may be loaded as if it were a "normal" or an EFI-stubbed kernel. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240304190038.3486881-87-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-23 12:44:00 +0000