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* ddr_spd: Fix mod_ranks test张忠山2019-04-101-1/+1
| | | | | | | ((x & 0x10) == 1) can never be true. Test for the bit at 0x10 instead. Signed-off-by: 张忠山 <zzs213@126.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr_spd: Add function to read eepromSascha Hauer2019-03-041-0/+82
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr_spd: Update from U-BootSascha Hauer2019-03-041-24/+98
| | | | | | | | | | | This updates the ddr_spd.h header file from U-Boot-2019.01 with some small changes: - typedefs are removed - "_s" suffix from struct types removed - remove unnecessary "extern" from function declarations Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* crc: import crc_itu_t() from kernelSascha Hauer2019-03-041-1/+1
| | | | | | | | Our cyc_crc16() function is the same function as crc_itu_t() in the Linux kernel. Import and use crc_itu_t() from the Kernel for consistency. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr_spd: remove unused arrayOleksij Rempel2018-11-191-2/+0
| | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ddr_spd: add routine for printing DDR2 SPD contents in human-readable formatAlexander Smirnov2015-07-141-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ---=== SPD EEPROM Information ===--- EEPROM Checksum of bytes 0-62 OK (0xDF) Total number of bytes in EEPROM 256 Fundamental Memory type DDR2 SDRAM SPD Revision 1.2 ---=== Memory Characteristics ===--- Maximum module speed 800 MHz (PC2-6400) Size 2048 MB Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 Ranks 2 SDRAM Device Width 8 bits Module Height 30.0 mm Module Type SO-DIMM (67.6 mm) DRAM Package Planar Voltage Interface Level SSTL 1.8V Module Configuration Type No Parity Refresh Rate Reduced (7.8 us) - Self Refresh Supported Burst Lengths 4, 8 Supported CAS Latencies (tCL) 6T tCL-tRCD-tRP-tRAS 6-6-6-18 as DDR2-800 Minimum Cycle Time 2.5 ns at CAS 6 Maximum Access Time 0.40 ns at CAS 6 Maximum Cycle Time (tCK max) 8 ns ---=== Timing Parameters ===--- Address/Command Setup Time Before Clock (tIS) 0.17 ns Address/Command Hold Time After Clock (tIH) 0.25 ns Data Input Setup Time Before Strobe (tDS) 0.05 ns Data Input Hold Time After Strobe (tDH) 0.12 ns Minimum Row Precharge Delay (tRP) 15.00 ns Minimum Row Active to Row Active Delay (tRRD) 7.50 ns Minimum RAS# to CAS# Delay (tRCD) 15.00 ns Minimum RAS# Pulse Width (tRAS) 45.00 ns Write Recovery Time (tWR) 15.00 ns Minimum Write to Read CMD Delay (tWTR) 7.50 ns Minimum Read to Pre-charge CMD Delay (tRTP) 7.50 ns Minimum Active to Auto-refresh Delay (tRC) 60.00 ns Minimum Recovery Delay (tRFC) 127 ns Maximum DQS to DQ Skew (tDQSQ) 0.20 ns Maximum Read Data Hold Skew (tQHS) 0.30 ns ---=== Manufacturing Information ===--- Manufacturer JEDEC ID 7f 98 00 00 00 00 00 00 Manufacturing Location Code 0x05 Part Number Manufacturing Date 2014-W47 Assembly Serial Number 0x43266892 Signed-off-by: Alexander Smirnov <alllecs@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* common: DDR3 SPD verification supportRenaud Barbier2014-03-181-0/+24
| | | | | | | | | Add DDR3 SPD verification support for use by the PPC 8xxx DDR driver. This is based on the equivalent files from U-Boot version git-be937b5. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* common: DDR2 SPD checksum.Renaud Barbier2013-06-271-0/+39
The code calculates the DDR2 SPD checksum as per JEDEC standard No 21-C Appendix X (revision 1.2) The code is based on the equivalent files from U-Boot version git-a71d45d. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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