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* clk: mux: Support mux specific flagsSascha Hauer2019-03-111-8/+11
| | | | | | | We'll need mux specific flags in the future, so add a parameter to the mux initialization functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: divider: pass divider flagsSascha Hauer2019-03-112-7/+9
| | | | | | | The generic clk divider needs clock flags and divider flags. Fix prototypes to take both as separate arguments. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Remove trailing whitespaces and tabsAlexander Shiyan2019-01-211-1/+1
| | | | | | | Just a cleanup over barebox tree Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: sync imx8mq clock driver with upstream kernelLucas Stach2019-01-152-277/+265
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: add imx8mq composite clockLucas Stach2019-01-153-0/+184
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx5: add di_predLucas Stach2018-12-131-0/+3
| | | | | | | | | This was missing, so the default external DI clock source on i.MX51 was missing. Also set the divider to a division ratio of 1 initially, to avoid complicating the logic in the IPU driver further. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/missing-prototypes'Sascha Hauer2018-12-071-8/+1
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| * clk: imx: Avoid missing prototype warningsSascha Hauer2018-11-121-8/+1
| | | | | | | | | | | | | | clk_gate2_free() is unused, so remove it. clk_gate2_alloc() is only used locally, so make it static. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2018-12-071-0/+9
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| * | ARM: i.MX5 clock: add clock provider supportMichael Grzeschik2018-11-191-0/+9
| |/ | | | | | | | | | | | | | | Currently it is impossible to get clks with clk_get(&clk, "name"); on the mx5 platform. Change that by adding clk-imx5 as clk_provider. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / clk: imx: cpu: avoid use after free on errorOleksij Rempel2018-11-191-1/+3
|/ | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: clk: imx5: Make locally used functions staticSascha Hauer2018-10-231-3/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX8MQ: Add missing IMX8MQ_CLK_TMU_ROOT clockAndrey Smirnov2018-09-241-0/+1
| | | | | | | Add missing IMX8MQ_CLK_TMU_ROOT clock needed for CPU thermal sensor. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX8MQ: Bump refcounters of various important clocksAndrey Smirnov2018-09-241-0/+12
| | | | | | | | | Bump refcounters of various important clocks in order to make sure their parents are not disabled during clock re-configuration added by commits that follow. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-sccg-pll: Remove leftover debug outputAndrey Smirnov2018-08-311-2/+0
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2018-07-092-18/+0
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| * mtd: gpmi-nand: Make sure clock is disabled during rate changeSascha Hauer2018-07-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX6 GPMI Nand controller the clock must be disabled during a rate change. Otherwise glitches on the clock line may occur which result in errors like: MXS NAND: Error sending command MXS NAND: DMA read error There were previous attempts to fix this. One is in: 54961378f0 imx6: clk: Gate off ENFC clock before setting clock rate This patch added a clk_disable() right before the rate change. Since a clk_disable() on a disabled clk is a no-op, the patch added a clk_enable() to the i.MX6 clk driver in the hope that the clk is enabled in the nand driver probe and the clk_disable() really takes place. This patch doesn't work. First of all it enabled the enfc_podf clk which was not the one that was actually disabled in the nand driver, resulting in the nand drivers call to clk_disable() still being a no-op. Then this patch also only works only on the classic i.MX6 which was the only one supported at that time, but not on the i.MX6UL, i.MX6SX and i.MX6SL which have a separate clk driver. Instead of adding more quirks to the other i.MX6 clk drivers, fix this in the GPMI driver. We no longer call clk_disable() on a disabled clk, but instead do a clk_enable() first which makes sure the hardware state is synchronized to the usage count and the following clk_disable() is really effective. At the same time we can (and actually must) remove the quirk in the i.MX6 clk driver. Also add clk_disable()/clk_enable() around another rate change in the GPMI driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: imx: remove unused clk_gate2_invertedSascha Hauer2018-07-061-17/+0
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | dts: update to v4.18-rc1Sascha Hauer2018-06-221-9/+8
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clock: Add i.MX8MQ clock driverSascha Hauer2018-06-115-0/+1078
| | | | | | | | | | | | | This is based on Lucas' patch sent as "[PATCH v2 4/4] clk: imx: add clock driver for i.MX8MQ CCM" to the mailing list. It will likely need some rework before it is finally merged, so apply the reworks here before merging into barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [andrew.smirnov@gmail.com: Fix pll type for IMX8MQ_VIDEO2_PLL1] Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX6: Fix enfc_sel for i.MX6dqpSascha Hauer2018-04-161-1/+18
| | | | | | | | The plus SoC variants have some differences in the clock controller. For now fix the NAND controller clock. There are more differences that might be relevant, but for now are left for a future excercise. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX6: Adjust GPMI parent clockSascha Hauer2018-04-121-0/+7
| | | | | | | | | | Based on the corresponding Kernel code: The gpmi needs 100MHz frequency in the EDO/Sync mode, We can not get the 100MHz from the pll2_pfd0_352m. So choose pll2_pfd2_396m as enfc_sel's parent. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: Port NAND clock setup code from LinuxAndrey Smirnov2018-04-032-2/+10
| | | | | | | | | Port Linux kernel commit 22039d150f716e4e ("clk: imx7d: create clocks behind rawnand clock gate") in order to correctly initialize clocks necessary for APBH DMA block to be functional on i.MX7 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx25: clk: add rngb clockSteffen Trumtrar2018-02-091-2/+3
| | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
* clk: imx: cpu: don't store the address of a function parameterUwe Kleine-König2017-08-151-2/+10
| | | | | | | | | | | | | | | The function imx_clk_cpu takes a const char *parent_name as second paramter. The implementation introduced in commit 9a89ed9d281e then uses the address of this function parameter to assign clk.parent_names. This is an address on the stack that is saved in the clk tree and of course this is easily overwritten by later execution paths of barebox. Without this fix the clk_dump command reproducibly crashes on i.MX7 (which is the only SoC that makes use of imx_clk_cpu()). Fixes: 9a89ed9d281e ("clk: imx: Add clk-cpu support") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* Merge branch 'for-next/imx'Lucas Stach2017-07-311-11/+0
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| * clk: i.MX7: Remove unused UART clocks arrayAndrey Smirnov2017-07-301-11/+0
| | | | | | | | | | | | | | | | | | Remove what looks like unused leftover from analogous Linux kernel code. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* | i.MX: clk-pllv3: Initially disable PLL_BYPASS bitPhilipp Zabel2017-07-121-0/+5
|/ | | | | | | | | | | | | | | | | | | | | | Commit cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit") overreached a bit by removing the code that disables the PLL_BYPASS bit for all architectures instead of making an exception for Vybrid and i.MX6SL. This causes the USB controller on i.MX6Q to run at bypass frequency and fail: barebox@Boundary Devices i.MX6 Quad Nitrogen6x Board:/ usb usb: USB: scanning bus for devices... usb: Bus 001 Device 001: ID 0000:0000 EHCI Host Controller imx-usb 2184200.usb: port(0) reset error This patch adds code to unconditionally disable the PLL_BYPASS bit initially, when the PLL clocks are registered. Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Fixes: cbff8031b491 ("i.MX: clk-pllv3: Do not touch PLL_BYPASS bit") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* i.MX: clk: Remove imx_clk_pllv3_locked()Andrey Smirnov2017-06-213-30/+14
| | | | | | | | | | Remove imx_clk_pllv3_locked() which was introduced for the sake of Vybrid platform. The same effect (waiting on 'locked' bit) can be achived with vanilla clk_pllv3_enable/disable, which make said function unnecessary. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX: clk-pllv3: Do not touch PLL_BYPASS bitAndrey Smirnov2017-06-211-2/+0
| | | | | | | | | | | | | | | | Do not touch PLL_BYPASS bit as a part of clk_pll3_enable/disable execution. For a number of platforms (e.g. Vybrid, i.MX6SL) PLL_BYPASS is specified as a bit controlling a clock MUX represented by a dedicated 'struct clk'. Altering that bit as a part of clk_pll3_enable/disable is equivalent to calling clk_set_parent() and it makes in the following code: clk_enable(clk_disable(<some pll>)) change clock chain instead of being a no-op. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk-vf610: Mark all of CCSR muxes with CLK_OPS_PARENT_ENABLEAndrey Smirnov2017-06-211-6/+6
| | | | | | | | | | | | | | | As per VYBRIDRM.pdf, p. 673: "... When switching clock sources on GL MUX, both active and target clock sources must be active..." So mark all of the clock muxes controlled by CCM_CSSR with CLK_OPS_PARENT_ENABLE to satisfy that requirement. Experiment shows that failing to do so would result in failure (in some cases CPU hang). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX6ul: Add Clock support for i.MX6ullStefan Riedmueller2017-05-171-11/+62
| | | | | | | From linux-4.10 clock support, only skipped some unnecessary clocks Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX50 clock: add clock for USB physbaseAlexander Kurz2017-04-241-0/+1
| | | | | | | | Add the USB physbase clock entry for i.MX50 SoC to enable USB device creation via DT. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2017-03-132-6/+2
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| * drivers: clk: clk-imx6.c: Don't gate LDB and IPUsDavid Jander2017-03-091-4/+1
| | | | | | | | | | | | | | | | | | | | | | Depending on CONFIG_DRIVER_VIDEO_IMX_IPUV3 to decide whether to gate IPU clocks or not is rather fragile. Any inadvertent dependency on the IPU (like setting the NoC AQoS registers for i.MX6QP) will result in a freeze if CONFIG_DRIVER_VIDEO_IMX_IPUV3 is disabled. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: imx: clk-imx6ul: Use anatop_base pointer for consistencyRobin van der Gracht2017-03-061-2/+1
| | | | | | | | | | | | | | | | The anatop_base pointer was unused, but instead of removing it, assign and use it for readability like clk-imx6 and clk-imx6sx do. Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx: clk-imx6ul: Fixed conditional for enabling USB phy clocksRobin van der Gracht2017-03-031-1/+1
|/ | | | | Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: setup ethernet clocksSascha Hauer2017-02-061-0/+11
| | | | | | | Reparent ethernet clocks so that they can be used by the fec driver. The values are the same as U-Boot uses. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: do not register PLL bypass clocks as separate clocksSascha Hauer2017-02-061-119/+85
| | | | | | | | | | | | | In the Kernel the bypass bits in the PLLs are now registered as separate clocks and are no longer handled in the PLL code. In barebox we haven't made this step and there currently seems to be no reason to do so. This means that the bypass bits are currently modified in both the PLL driver and in the separate clocks which does not work properly. Drop all the bypass clocks to let the bypass bits be handled in the PLL driver exclusively. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: Fix ethernet clocksSascha Hauer2017-02-062-4/+17
| | | | | | | | | | | | | The original clock code from Linux registers some gates at base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference manual and do not seem to have any effect on the hardware. The reference manual lists clocks at 0x4700 and 0x4710 which Linux does not control at all. These clocks really do have an effect on the hardware and are needed for ethernet support. Register the existing clocks rather than the made up clocks to support ethernet. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: do clock reparenting when all clocks are initializedSascha Hauer2017-02-061-8/+23
| | | | | | | | | By the time the i.MX7 clock driver probes the fixed clocks which are the roots of the clock tree are not yet present, so reparenting especially to one of the fixed clocks does not work. Move the tree setup to a later initcall when the fixed clocks are there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessarySascha Hauer2017-02-061-4/+4
| | | | | | CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: clk-gate2: Allow to pass flagsSascha Hauer2017-02-062-9/+10
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX: Add i.MX6SL supportAlexander Kurz2017-02-021-0/+1
| | | | | | | | | | | | | Most i.MX6SL infrastructure is already covered in barebox by general i.MX6 support. Missing infrastructure provided in separate commits are * SoC type detection * Clock infrastructure Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc and the remaining bits and pieces to provide barebox i.MX6SL SoC support. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX6SL: import clock infrastructure from linuxAlexander Kurz2017-02-021-0/+329
| | | | | | | | | | | | | | Import i.MX6SL clock infrastructure from linux clk-imx6sl.c To save space, clocks beeing unlikely usefull for bootloader purposes (SSI, SPDIF, EXTERN_AUDIO) were not imported. Further, the fixup code from linux mainline commits a49e6c4b8204 ("ARM: imx: add common clock support for fixup mux") cbe7fc8aaeef ("ARM: imx: add common clock support for fixup div") was ignored for this commit. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX31 clk: add pll_ref_clk and MCU PLL bypass selectAlexander Kurz2017-01-261-5/+23
| | | | | | | | | | | The three MX31 PLL may be clocked from either CKIH or a frequency-multiplied derivate of CKIL generated by the Frequency Pre Multiplier FPM. Add the pll_ref_clk selection infrastructure and support for MCU PLL bypass to support clock switching and boards not clocked CKIH. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: Add missing USB clocksSascha Hauer2017-01-191-0/+3
| | | | | | The USB clocks are missing in the Kernel clock code. Add them here. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: Add clock support for i.MX7Juergen Borleis2017-01-193-0/+908
| | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: Add clk-cpu supportSascha Hauer2017-01-193-0/+114
| | | | | | Taken from the kernel as of 4.10-rc3. Needed for i.MX7 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: pllv3: Add support for the i.MX7 enet pllSascha Hauer2017-01-192-5/+19
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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