summaryrefslogtreecommitdiffstats
path: root/drivers/clk/rockchip/clk-pll.c
Commit message (Collapse)AuthorAgeFilesLines
* clk: rockchip: pll fix out of bounds readAhmad Fatoum2023-12-051-7/+9
| | | | | | | | | | | | parent_names[1] is only valid for PLLs that are not of the type pll_rk3328. Yet, the code references it anyway unconditionally, triggering a KASan error. Fix this by slightly reworking the code. This issue also seems to exist upstream in Linux. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231205081052.4145979-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: switch regmap.h include to linux/regmap.hAhmad Fatoum2023-10-261-1/+1
| | | | | | | | | | | | | | | Now that there are no longer any users of regmap.h in headers, let's switch all users in the source files to linux/regmap.h. That way, the only users of regmap.h whether directly or indirectly will be out-of-tree code, which will fail with an error if they are dependent on the old semantics of regmap_bulk_read and regmap_bulk_write. After a transitory period, we can then drop regmap.h. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231020071853.2826528-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: rockchip: add missing pll_rk3588_core handlingSascha Hauer2023-05-301-1/+2
| | | | | | | According to the reference manual the PLLs of type pll_rk3588_core also need the CLK_MUX_HIWORD_MASK. Add it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: rockchip: Add rk3588 supportSascha Hauer2023-05-231-5/+221
| | | | | | | This adds the rk3588 clk support from Linux-6.3-rc7 without much changes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: Rockchip: Fix arrays out of bounds accessSascha Hauer2023-03-091-2/+3
| | | | | | | | In rockchip_clk_register_pll() the number of parent_names is passed in num_parents. Do not access parent_names[1] when the array is not big enough. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: rockchip: Update to current LinuxSascha Hauer2021-06-091-107/+732
| | | | | | | | | | This updates the Rockchip clk code to Linux-5.13-rc1. The code is unchanged as much as possible. The pre- and post- change hooks are removed and also the notifier blocks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210602095507.24609-24-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: introduce struct clk_hwSascha Hauer2021-06-071-20/+20
| | | | | | | | | | | | | | | | | | | In Linux the ops in struct clk_ops take a struct clk_hw * argument instead of a struct clk * argument as in barebox. With this taking new clk drivers from Linux requires a lot of mechanical conversions. Instead of doing this over and over again swallow the pill once and convert the existing barebox code over to clk_hw. The implementation is a little different from Linux. In Linux struct clk is only known to the core clock code. In barebox struct clk is publically known and it is embedded into struct clk_hw. This allows us to still use struct clk members in the clock drivers which we currently still need, because otherwise this patch would be even bigger. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210602095507.24609-5-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: rename clk_register() to bclk_register()Sascha Hauer2021-06-071-2/+2
| | | | | | | | | | | | Linux has a clk_register() function with a different semantics than barebox. Rename this function to bclk_register() so that we later can introduce a clk_register() function with the same semantics as Linux. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20210602095507.24609-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: include <linux/math64.h> wrapper instead of <asm-generic/div64.h>Ahmad Fatoum2021-02-191-1/+1
| | | | | | | | | | | <asm-generic/div64.h> isn't meant for direct usage as <asm/div64.h> may override this on a per-architecture basis. We don't do that currently, but in the future we might. Include the <linux/math64.h> instead. No functional change. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: migrate to SPDX-License-Identifier useAhmad Fatoum2020-04-151-10/+1
| | | | | | | | | | | | Some of these are a product of source sync with Linux, the other were done with macro assistance by searching for /later/, deleting license text, adding appropriate SPDX-License-Identifier and manual post-review. Devices without a license indicated where assumed GPL-2.0-only according with the project's license. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: mux: Support mux specific flagsSascha Hauer2019-03-111-1/+2
| | | | | | | We'll need mux specific flags in the future, so add a parameter to the mux initialization functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: clk: rk3188: don't set same clk rate twiceperachet7@gmail.com2018-11-091-0/+3
| | | | | | | | | | | We found setting a clock rate which has already been set, rk3188 (radxa rock pro) bails out. This is a quick fix only. Underlying situation not (yet) investigated: why it is even trying to set it to the same rate again. It remains to state that some but not all rrpro boards exhibit this behaviour, no other rk3188 boards have been tested. Signed-off-by: P. Rachet <perachet7@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Rockchip: Update clk driver from Linux kernel for use with newer DTSAndrey Panov2015-03-051-0/+368
Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>