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When building for Cyclone5 SoCFPGA, the socfpga_a10_pll_init(),
socfpga_a10_perith_init() and socfpga_a10_gate_init() functions are
defined as dummy functions returning ERR_PTR(-ENOSYS). They are defined
with external linkage. With '-Wmissing-prototypes' GCC warns about
externally linked function definitions with no preceding prototype.
Define them as 'static inline' to avoid the compiler warnings.
(Note: Arria10 uses non-dummy versions of these functions declared
'extern' but defined elsewhere.)
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Arria10 has a (slightly) different clock controller than the
Cyclone5. Add new drivers for it.
This driver only reads out the setup and builds the clocktree,
it does not setup any clocks.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Prepare for Arria10 clock driver.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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