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* clk: mux: Support mux specific flagsSascha Hauer2019-03-111-1/+1
| | | | | | | We'll need mux specific flags in the future, so add a parameter to the mux initialization functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* driver: replace dev_request_mem_region with dev_request_mem_resourceSascha Hauer2016-03-073-9/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region doesn't work properly one some SoCs on which PTR_ERR() values clash with valid return values from dev_request_mem_region. Replace them with dev_request_mem_resource where possible. This patch has been generated with the following semantic patch: // <smpl> @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { ... - return PTR_ERR(io); -} + return PTR_ERR(iores); +} +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) - return PTR_ERR(io); -} + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { - ret = PTR_ERR(io); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { + ret = PTR_ERR(iores); ... } +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ identifier func; @@ func(...) { <+... struct resource *iores; -struct resource *iores; ...+> } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: don't enable UART clocks by defaultLucas Stach2014-11-043-14/+14
| | | | | | | | Now that we are registering a proper driver for the UARTs we no longer need to enable the clocks unconditionally. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: slow down MSELECT to 102MHzLucas Stach2014-11-042-2/+2
| | | | | | | | Don't know where I got the 204MHZ previously, but 102MHz is the official supported maximum. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra124: add PCIe clocksLucas Stach2014-11-041-0/+35
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra124: add PLLE setup functionsLucas Stach2014-11-042-3/+177
| | | | | | | | This adds functions to bring up the new style Tegra114+ PLL_E. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra30: add PCIe clocksLucas Stach2014-10-081-0/+31
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: add PLLE setup functionsLucas Stach2014-10-082-0/+122
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* resource: Let dev_request_mem_region return an error pointerSascha Hauer2014-09-163-6/+6
| | | | | | For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: add Tegra124 driverLucas Stach2014-06-052-0/+350
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: don't bug out on zero PLL postdivLucas Stach2014-06-051-2/+0
| | | | | | | | As the real value is 2^p a input value of 0 is actually valid. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: allow variable sized muxesLucas Stach2014-06-051-2/+4
| | | | | | | | Tegra124 extended the mux by 1bit to allow for more PLL sources. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra20: register i2c clocksLucas Stach2014-05-151-0/+13
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra30: register i2c clocksLucas Stach2014-05-151-0/+16
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: allow to register clocks with 16 bit dividerLucas Stach2014-05-152-7/+25
| | | | | | | | Some peripherals have a double wide divider in front of them. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: remove device reset hackLucas Stach2014-05-151-18/+0
| | | | | | | | | Now that we have a proper reset controller, it isn't necessary anymore to keep the device reset hack coupled to the clock. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: reset UARTS from clock controllerLucas Stach2014-05-154-0/+15
| | | | | | | | | | The console devices are the only ones that can't use the reset controller properly, as they get registered from platform code. Reset those devices from the clock controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* reset: add tegra reset controllerLucas Stach2014-05-154-1/+149
| | | | | | | | Allows us to drop the hack in the clock controller and implement proper reset at device level. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/tegra'Sascha Hauer2014-05-054-94/+462
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/dts/tegra20-colibri.dtsi arch/arm/dts/tegra20-paz00.dts arch/arm/dts/tegra20.dtsi drivers/clk/tegra/clk-periph.c
| * clk: tegra: add Tegra3 driverLucas Stach2014-04-232-1/+367
| | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra: consider new T30 clock registersLucas Stach2014-04-231-5/+15
| | | | | | | | | | | | | | | | | | Tegra3 has some new clocks and resets. The new registers don't form a linear range with the old ones. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra20: convert to dt-binding definesLucas Stach2014-04-071-88/+80
| | | | | | | | | | | | | | | | Allows to make relationship between DT and driver more explicit and avoids duplication. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: gate: add flags argument to clock gate constructorBeniamino Galvani2014-04-291-1/+1
|/ | | | | | | | This adds a clk_gate_flags argument to clock gate creation functions to allow the introduction of new clock gate modifiers. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-fixed-factor: pass flags to initializersSascha Hauer2014-03-281-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-gate: pass flags to initializersSascha Hauer2014-03-281-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-mux: pass clk flags from initializersSascha Hauer2014-03-281-1/+1
| | | | | | | struct clk has a flags field, let the clk-mux initializers set this field. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: add SDMMC clocksLucas Stach2013-12-041-0/+18
| | | | | | | Provide peripheral clocks for the SD controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: speed up system busLucas Stach2013-12-041-0/+7
| | | | | | | | | We run the system bus from the OSC clock during init, to avoid crashing the system while reconfiguring the PLLs. Switch to a more reasonable clock when we are done with this. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add peripheral clocksLucas Stach2013-07-024-0/+254
| | | | | | | | Only UART clocks are included for now, but the code should cover other peripherals needs, too. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* tegra: add new clock framework driverLucas Stach2013-07-027-0/+1307
This removes the existing Tegra CAR driver and replaces it with code ported from the Linux clock framework. In the current state only the relevant PLLs are supported, but this is no functional regression from the existing code. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-14 16:37:39 +0000