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path: root/drivers/clk/zynq
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* ARM: zynq: get ps_clk_rate from dtAssmann Kai2023-07-041-1/+3
* treewide: add MODULE_DEVICE_TABLE markersAhmad Fatoum2023-06-131-0/+1
* ARM: zynq: Move mach header files to include/mach/zynqSascha Hauer2023-03-061-1/+1
* Rename struct driver_d to driverSascha Hauer2023-01-101-1/+1
* Rename struct device_d to deviceSascha Hauer2023-01-101-1/+1
* Rename device_d::device_node to device_d::of_nodeSascha Hauer2023-01-101-2/+2
* clk: introduce struct clk_hwSascha Hauer2021-06-071-50/+50
* clk: rename clk_register() to bclk_register()Sascha Hauer2021-06-071-4/+4
* treewide: Use driver macroSascha Hauer2020-09-291-5/+1
* clk: migrate to SPDX-License-Identifier useAhmad Fatoum2020-04-152-12/+2
* clk: zynq: add QSPI reference clockLucas Stach2019-12-201-0/+3
* clk: zynq: remove clkdevsLucas Stach2019-11-111-9/+0
* clk: zynq: partially sync with LinuxLucas Stach2019-11-111-16/+71
* clk: zynq: fix up address from DTLucas Stach2019-11-111-1/+23
* clk: zynq: improve PLL enable handlingLucas Stach2019-11-111-1/+12
* clk: zynq: use base address of clock controllerLucas Stach2019-11-111-15/+15
* ARM: zynq: move clock controller driver to drivers/clkLucas Stach2019-11-112-0/+427
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 09:18:21 +0000