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* Merge branch 'for-next/rockchip' into nextnextSascha Hauer39 hours1-0/+10
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| * clk: rk3568: sync PLL rates with LinuxAhmad Fatoum11 days1-0/+10
| | | | | | | | | | | | | | | | | | The Linux driver has gained additional PLL rates since we last synchronized. Add their parameters to barebox as well. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240415053154.368546-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc' into nextSascha Hauer39 hours1-20/+67
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| * | commands: clk_dump: add json output optionAhmad Fatoum4 days1-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This formats the clock tree and the enable_count and rate of each clock into the JSON format. This is useful to run validation scripts against it that were originally written for Linux' /sys/kernel/debug/clk/clk_dump. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419060759.2590652-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: add flags parameter to clk_dump(_one)Ahmad Fatoum4 days1-14/+14
| |/ | | | | | | | | | | | | | | | | | | We currently customize dumping by means of a single verbose argument. Follow-up commit will want to customize the dumping further, so turn the verbose parameter into a general flags parameter. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419060759.2590652-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/dts' into nextSascha Hauer39 hours3-1/+23
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| * | clk: rockchip: rk3588: fix CLK_NR_CLKS usageSascha Hauer2024-04-023-1/+23
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox adoption of Linux commit 2dc66a5ab2c6: | clk: rockchip: rk3588: fix CLK_NR_CLKS usage | | CLK_NR_CLKS is not part of the DT bindings and needs to be removed | from it, just like it recently happened for other platforms. This | takes care of it by introducing a new function identifying the | maximum used clock ID at runtime. | | Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> | Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com | Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.barebox.org/20240402091926.4096972-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx: imx8mp: sync with Linux v6.9-rc3Ahmad Fatoum4 days2-35/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync is mainly done to pull in Linux commit c277ca155d2f0: | Author: Peng Fan <peng.fan@nxp.com> | AuthorDate: Sun Nov 1 19:23:54 2020 +0800 | | clk: imx8m: fix bus critical clk registration | | noc/axi/ahb are bus clk, not peripheral clk. | Since peripheral clk has a limitation that for peripheral clock slice, | IP clock slices must be stopped to change the clock source. | | However if the bus clk is marked as critical clk peripheral, the | assigned clock parent operation will fail. | | So we added CLK_SET_PARENT_GATE flag to avoid glitch. | | And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage | | Fixes: 936c383673b9e ("clk: imx: fix composite peripheral flags") | Reviewed-by: Abel Vesa <abel.vesa@nxp.com> | Reported-by: Abel Vesa <abel.vesa@nxp.com> | Signed-off-by: Peng Fan <peng.fan@nxp.com> | Link: https://lore.kernel.org/r/1604229834-25594-1-git-send-email-peng.fan@nxp.com | Signed-off-by: Stephen Boyd <sboyd@kernel.org> Without this, attempts to reparent e.g. noc_io would hang. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419061003.2590849-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx: composite-8m: fix muxing of core and bus clocksAhmad Fatoum4 days1-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX8M differntiates between three types of composite clocks (called slices): Core, Bus and IP (peripheral) clocks. How muxes are configured differs between these clocks, so the driver is populating a mux_ops variable to point at the correct struct clk_ops. Unfortunately, mux_ops wasn't actually used, leading to barebox hangs, depending on the assigned-clock-parents properties in the device tree. This oversight is likely due to the different prototypes of clk_register_composite and clk_hw_register_composite, the latter of which didn't exist when the driver was added. The API is available now, so sync the function with Linux to fix this issue. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419061003.2590849-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx: add IMX_COMPOSITE_CLK_FLAGS_DEFAULT macroAhmad Fatoum4 days1-2/+5
| | | | | | | | | | | | | | | | | | We use the same flags in two macros and will add one more instance in a follow-up commit, so factor them out into a macro like Linux does. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419061003.2590849-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx27: add watchdog clockSascha Hauer10 days1-0/+2
| | | | | | | | | | | | | | | | | | Since 87cad17964 the imxwd watchdog driver needs a clock to probe. Add this clock for i.MX27 to make the watchdog driver work again. Fixes: 87cad17964 ("watchdog: imxwd: get and enable clock") Link: https://lore.barebox.org/20240416063126.1345967-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx27: add nand clockSascha Hauer10 days1-0/+1
|/ | | | | | | | | The NAND clock is currently missing. The NAND driver doesn't use it currently, but will be using it later once we update the driver. Add this missing clock. Link: https://lore.barebox.org/20240416063126.1345967-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: sync drivers with LinuxAhmad Fatoum2024-02-1630-1461/+3557
| | | | | | | | | | | | | | | | | | | During bug hunt of a clocking issue that ultimately turned out to be unrelated, I resynced AT91 clk support with Linux. The changes look more extensive than they really are, because I first imported the clock drivers before a major overhaul of the barebox clock framework to be more compatible with the more recent kernel API changes. Most of the diff is due to that, but this resync also fixes at least a USB issue for the at91rm9200 and adds support for the new SAMA7 SoC as well as more clocks for the SAM9x60. Both these SoCs aren't supported by barebox yet, but this at least adds clock driver support. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240215121837.251013-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2024-01-232-3/+22
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| * clk: select CLKDEV_LOOKUP from COMMON_CLKAhmad Fatoum2024-01-191-0/+1
| | | | | | | | | | | | | | | | | | | | All platforms that select COMMON_CLK also select CLKDEV_LOOKUP, therefore just select it in drivers/clk/Kconfig and drop the CLKDEV_LOOKUP all over the place. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240118090718.1314156-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: make COMMON_CLK a visible symbolAhmad Fatoum2024-01-191-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far, we expected platforms to select COMMON_CLK if they have a clock controller that's covered by the common clk framework and HAVE_CLK if they have a legacy clock driver. With the addition of SCMI clocks, platforms, especially virtualized ones, that previously didn't need clock support may now want access to them. Instead of having to select COMMON_CLK from such platforms on the off-chance that SCMI clocks may need to be used, just make COMMON_CLK user visible, so it can be selected as needed. As COMMON_CLK needs to conflict with legacy clock support, we also add a symbol for that and start selecting it where appropriate, Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240118090718.1314156-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * treewide: mark linker list elements with __ll_elemAhmad Fatoum2024-01-111-2/+1
| | | | | | | | | | | | | | | | | | To fix build with clang while using ASAN, define all linker list elements with __ll_elem. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240103101748.2629927-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: layerscape: increase PLL divider arraySascha Hauer2024-01-101-1/+2
| | | | | | | | | | | | | | | | Newer Layerscape SoCs like the LS1028a have more PLL dividers, increase the divider array to accomodate this. Link: https://lore.barebox.org/20240109161527.3237581-18-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: layerscape: add support for ls1028aSascha Hauer2024-01-021-0/+69
| | | | | | | | | | Link: https://lore.barebox.org/20231219132122.7964-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: layerscape: move chipinfo_ls1012a further upSascha Hauer2024-01-021-7/+7
|/ | | | | | | Cosmetic change to keep the chipinfo entries ordered. Link: https://lore.barebox.org/20231219132122.7964-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/op-tee'Sascha Hauer2023-12-1812-55/+4596
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| * clk: add STM32MP13 clock and reset driversAhmad Fatoum2023-12-059-0/+4364
| | | | | | | | | | | | | | | | | | | | | | The reset and clock control peripheral of the STM32MP13 is with publicly available firmware exclusively handled by the secure world and normal world needs to employ SCMI to interact with OP-TEE to toggle clocks for it. Import the Linux driver to facilitate this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064947.2207726-10-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: add struct clk_init_data::parent_hwsAhmad Fatoum2023-12-051-14/+45
| | | | | | | | | | | | | | | | | | | | | | For cases where all clock parents are internal to the clock controller, parent_hws allows specifying direct pointers to the clk_hw structures instead of globally unique names. Add support for this to barebox to be used by the incoming STM32MP13 clock driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064947.2207726-8-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: implement clk clk_hw_get_parent_by_indexAhmad Fatoum2023-12-051-4/+21
| | | | | | | | | | | | | | | | | | | | This is the inverse operation to clk_get_parent_index and is already implemented inline in clk_get_parent. Factor that code out for use by the incoming STM32MP13 clock driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064947.2207726-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: divider: implement divider_[ro_]round_rate_parentAhmad Fatoum2023-12-051-1/+34
| | | | | | | | | | | | | | | | | | These functions will be used in the incoming STM32MP13 clock driver support. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064947.2207726-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: divider: implement CLK_DIVIDER_ALLOW_ZEROAhmad Fatoum2023-12-051-0/+6
| | | | | | | | | | | | | | | | | | | | We already support CLK_DIVIDER_ONE_BASED and incoming STM32MP13 clock support can have clock dividers evaluate to zero. Add support for CLK_DIVIDER_ALLOW_ZERO analogously to Linux. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064947.2207726-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: factor out clk_hw_get_parent_indexAhmad Fatoum2023-12-051-11/+44
| | | | | | | | | | | | | | | | | | | | | | clk_ops::set_parent passes the parent as an index, so clk_set_parent needs to determine the index. Linux provides this information via clk_hw_get_parent_index and some drivers depend on this, so factor out the code in question in barebox as well. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064947.2207726-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: stm32mp1: build only when STM32MP15 support is enabledAhmad Fatoum2023-12-052-1/+6
| | | | | | | | | | | | | | | | | | | | The stm32mp1 clock driver is only used on the STM32MP15 and won't be reused for the STM32MP13, so let's make it dependent on ARCH_STM32MP157 instead of CONFIG_ARCH_STM32MP. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064947.2207726-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * firmware: arm_scmi: sync with Linux v6.6Ahmad Fatoum2023-12-051-24/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since our initial import of the ARM SCMI infrastructure in Linux, the upstream driver has been extended to support SCMI via OP-TEE and arm_ffa as well and also gained support for more function, including sensors and power domains, which may be useful in barebox going forward. Let's sync with Linux again and add the OP-TEE transport alongside the existing SMC-based transport. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231127064034.2206788-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: rockchip: pll fix out of bounds readAhmad Fatoum2023-12-051-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | parent_names[1] is only valid for PLLs that are not of the type pll_rk3328. Yet, the code references it anyway unconditionally, triggering a KASan error. Fix this by slightly reworking the code. This issue also seems to exist upstream in Linux. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231205081052.4145979-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: ti-sci: fix build failure without TI_SCI_PROTOCOLAhmad Fatoum2023-12-052-1/+10
|/ | | | | | | | | | The SCI clk driver has an unconditional reference to ti_sci_get_handle(), but no dependency is specific in the Kconfig. Add a dependency and change defaults, so it's enabled by default. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231204165238.1131311-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/k3'Sascha Hauer2023-11-272-0/+631
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| * clk: Add K3 SCI clock driverSascha Hauer2023-11-062-0/+631
| | | | | | | | | | | | | | | | Add support for clocks on TI K3 SoCs. The code is based on Linux-6.5-rc3. Link: https://lore.barebox.org/20230803105003.4088205-11-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx: clk-fracn-gppll: make usable from PBLSascha Hauer2023-11-172-142/+21
| | | | | | | | | | | | | | | | | | The PBL code needs to adjust the DDR PLL before setting up DDR. Factor out the PLL setup code as a static inline function for PBL usage. Link: https://lore.barebox.org/20231110125800.1901232-8-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Add i.MX93 clock supportSascha Hauer2023-11-176-0/+1168
|/ | | | | | | Based on Linux i.MX93 clock support as of Linux-6.6 Link: https://lore.barebox.org/20231110125800.1901232-7-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: switch regmap.h include to linux/regmap.hAhmad Fatoum2023-10-2634-34/+34
| | | | | | | | | | | | | | | Now that there are no longer any users of regmap.h in headers, let's switch all users in the source files to linux/regmap.h. That way, the only users of regmap.h whether directly or indirectly will be out-of-tree code, which will fail with an error if they are dependent on the old semantics of regmap_bulk_read and regmap_bulk_write. After a transitory period, we can then drop regmap.h. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20231020071853.2826528-12-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2023-09-251-2/+2
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| * clk: have clk_get always return -ENOENT on missing clockAhmad Fatoum2023-09-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, clk_get(dev, NULL) returns -ENOENT on missing clock, but clk_get(dev, "missing-named-clock") returns -EINVAL. This went by unnoticed so far as most consumers either require a clock or don't, but with the addition of clk_get_optional, it's important that clk_get() return value is uniform. Therefore align clk_get with Linux and always fall through to clk_get_sys() if getting clock over DT is not possible. Failing clk_get_sys() returns -ENOENT always, ensuring we can't end up with -EINVAL as before while keeping of_clk_get_by_name return value as it is under Linux. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230918170458.121957-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx8mp: Drop SAI4 clkSascha Hauer2023-09-121-5/+0
|/ | | | | | | | The hardware does not have a SAI4 instance, so remove handling it from the clock driver. This avoids a regression with the next dts update where the IMX8MP_CLK_SAI4 define is removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nvmem: ocotp: handle too early calls into ocotp driver gracefullyAhmad Fatoum2023-07-281-1/+4
| | | | | | | | | | | | | HAB code calls into OCOTP driver by relying on a global imx_ocotp variable that's populated on driver probe. For board code that calls a HAB function to early, this may end up dereferencing a NULL pointer, so let's return -EPROBE_DEFER in that case or if deep probe is enabled, just probe the OCOTP directly. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230726192718.911735-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: zynq: get ps_clk_rate from dtAssmann Kai2023-07-041-1/+3
| | | | | | | | | | | | | | | | This adds a barebox-specific binding to overwrite the PS clock frequency. Currently the ps_clk_rate is locked to 33.3MHz. Introduce a devicetree property "ps-clock-frequency" that specifies this clock. If the property is found, overwrite ps_clk_rate otherwise stay at the default 33.3MHz Signed-off-by: Assmann Kai (BEG/MSD-NE2) <Kai.Assmann@de.bosch.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20230626103756.983193-1-s.trumtrar@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Print device nodes with %pOFSascha Hauer2023-07-034-14/+14
| | | | | | | We have the %pOF format specifier for printing device nodes. Use it where appropriate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rockchip'Sascha Hauer2023-06-222-2/+3
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| * clk: clk-divider: fix CLK_DIVIDER_HIWORD_MASK flagSascha Hauer2023-05-301-1/+1
| | | | | | | | | | | | | | The CLK_DIVIDER_HIWORD_MASK flag is in divider->flags, not in the generic clock flags. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: rockchip: add missing pll_rk3588_core handlingSascha Hauer2023-05-301-1/+2
| | | | | | | | | | | | | | According to the reference manual the PLLs of type pll_rk3588_core also need the CLK_MUX_HIWORD_MASK. Add it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | treewide: add MODULE_DEVICE_TABLE markersAhmad Fatoum2023-06-1336-0/+39
|/ | | | | | | | | | | | | | | | Syncing device trees with Linux upstream can lead to breakage, when the device trees are switched to newer bindings, which are not yet supported in barebox. To make it easier to spot such issues, we want to start applying some heuristics to flag possibly problematic DT changes. One step towards being able to do that is to know what nodes barebox actually consumes. Most of the nodes have a compatible entry, which is matched by an array of of_device_id, so let's have MODULE_DEVICE_TABLE point at it for future extraction. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230612125908.1087340-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32mp'Sascha Hauer2023-05-241-2/+3
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| * clk: bulk: return -EPROBE_DEFER in silenceAhmad Fatoum2023-05-021-2/+3
| | | | | | | | | | | | | | | | | | -EPROBE_DEFER is only an error if driver core doesn't expect it. Change it, so error message is only printed for other kinds of errors. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230421100642.2867651-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/rockchip'Sascha Hauer2023-05-246-33/+3757
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| * | clk: rockchip: Add rk3588 supportSascha Hauer2023-05-236-33/+3757
| |/ | | | | | | | | | | | | This adds the rk3588 clk support from Linux-6.3-rc7 without much changes. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 22:36:02 +0000