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* Merge branch 'for-next/socfpga'Sascha Hauer2017-05-057-2/+574
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| * clk: socfpga: add arria10 clk driversSteffen Trumtrar2017-05-036-1/+572
| | | | | | | | | | | | | | | | | | | | | | Arria10 has a (slightly) different clock controller than the Cyclone5. Add new drivers for it. This driver only reads out the setup and builds the clocktree, it does not setup any clocks. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: socfpga: move driver to subdirectorySteffen Trumtrar2017-05-033-1/+2
| | | | | | | | | | | | | | Prepare for Arria10 clock driver. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | ARM: i.MX50 clock: add clock for USB physbaseAlexander Kurz2017-04-241-0/+1
|/ | | | | | | | Add the USB physbase clock entry for i.MX50 SoC to enable USB device creation via DT. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2017-04-072-4/+0
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| * clk: No-op CLK_OF_DECLARE if not enabledAndrey Smirnov2017-03-302-4/+0
| | | | | | | | | | | | | | | | | | Instead of wrapping each defenition of CLK_OF_DECLARE hook with preprocessor guards, change the definition of CLK_OF_DECLARE to expand into no-op if COMMON_CLK_OF_PROVIDER is not enabled. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mips'Sascha Hauer2017-04-071-3/+3
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| * | clk: clk-gate-shared: fix "no previous prototype" warningAntony Pavlov2017-03-301-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes these compiler's warnings: drivers/clk/clk-gate-shared.c:72:13: warning: no previous prototype for 'clk_gate_shared_alloc' [-Wmissing-prototypes] struct clk *clk_gate_shared_alloc(const char *name, const char *parent, const char *companion, ^ drivers/clk/clk-gate-shared.c:89:6: warning: no previous prototype for 'clk_gate_shared_free' [-Wmissing-prototypes] void clk_gate_shared_free(struct clk *clk) ^ Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: Port at91 DT clock codeAndrey Smirnov2017-03-3018-0/+4145
|/ | | | | | | | Port at91 DT clock code from Linux 4.9-rc3. Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2017-03-132-6/+2
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| * drivers: clk: clk-imx6.c: Don't gate LDB and IPUsDavid Jander2017-03-091-4/+1
| | | | | | | | | | | | | | | | | | | | | | Depending on CONFIG_DRIVER_VIDEO_IMX_IPUV3 to decide whether to gate IPU clocks or not is rather fragile. Any inadvertent dependency on the IPU (like setting the NoC AQoS registers for i.MX6QP) will result in a freeze if CONFIG_DRIVER_VIDEO_IMX_IPUV3 is disabled. Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: imx: clk-imx6ul: Use anatop_base pointer for consistencyRobin van der Gracht2017-03-061-2/+1
| | | | | | | | | | | | | | | | The anatop_base pointer was unused, but instead of removing it, assign and use it for readability like clk-imx6 and clk-imx6sx do. Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/at91'Sascha Hauer2017-03-135-4/+44
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| * | clk: Make COMMON_CLK_OF_PROVIDER depend on OFTREEAndrey Smirnov2017-03-095-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make COMMON_CLK_OF_PROVIDER depend on OFTREE, this way checking for: defined(CONFIG_OFTREE) && defined(CONFIG_COMMON_CLK_OF_PROVIDER) can be simplified to just: defined(CONFIG_COMMON_CLK_OF_PROVIDER) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: Port two helper functions from LinuxAndrey Smirnov2017-03-091-0/+39
| |/ | | | | | | | | | | | | Port of_clk_get_parent_count() and of_clk_parent_fill() from Linux. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: imx: clk-imx6ul: Fixed conditional for enabling USB phy clocksRobin van der Gracht2017-03-031-1/+1
|/ | | | | Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: setup ethernet clocksSascha Hauer2017-02-061-0/+11
| | | | | | | Reparent ethernet clocks so that they can be used by the fec driver. The values are the same as U-Boot uses. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: do not register PLL bypass clocks as separate clocksSascha Hauer2017-02-061-119/+85
| | | | | | | | | | | | | In the Kernel the bypass bits in the PLLs are now registered as separate clocks and are no longer handled in the PLL code. In barebox we haven't made this step and there currently seems to be no reason to do so. This means that the bypass bits are currently modified in both the PLL driver and in the separate clocks which does not work properly. Drop all the bypass clocks to let the bypass bits be handled in the PLL driver exclusively. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: Fix ethernet clocksSascha Hauer2017-02-062-4/+17
| | | | | | | | | | | | | The original clock code from Linux registers some gates at base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference manual and do not seem to have any effect on the hardware. The reference manual lists clocks at 0x4700 and 0x4710 which Linux does not control at all. These clocks really do have an effect on the hardware and are needed for ethernet support. Register the existing clocks rather than the made up clocks to support ethernet. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: Add support for shared gatesSascha Hauer2017-02-062-1/+125
| | | | | | | | | | | Sometimes a single software control knob controls multiple gates in hardware. This patch adds support for shared gates which help coping this situation. The first gate is registered with the hardware gate as usual, the others are registered as shared gates which does not have hardware control itself, but only switches the real hardware gate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: do clock reparenting when all clocks are initializedSascha Hauer2017-02-061-8/+23
| | | | | | | | | By the time the i.MX7 clock driver probes the fixed clocks which are the roots of the clock tree are not yet present, so reparenting especially to one of the fixed clocks does not work. Move the tree setup to a later initcall when the fixed clocks are there. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessarySascha Hauer2017-02-061-4/+4
| | | | | | CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: clk-gate2: Allow to pass flagsSascha Hauer2017-02-062-9/+10
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: implement CLK_OPS_PARENT_ENABLESascha Hauer2017-02-061-4/+27
| | | | | | | | Some clocks may only be modified when their parent clocks are enabled. The kernel has the CLK_OPS_PARENT_ENABLE flag for this purpose. Implement it for barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: Keep enable count consistent over reparentSascha Hauer2017-02-061-6/+15
| | | | | | | | When reparenting a clock we have to make sure the new parent is enabled when the clock was enabled on the old parent. Also we have to decrease the old parents use counter when the clock was enabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX: Add i.MX6SL supportAlexander Kurz2017-02-021-0/+1
| | | | | | | | | | | | | Most i.MX6SL infrastructure is already covered in barebox by general i.MX6 support. Missing infrastructure provided in separate commits are * SoC type detection * Clock infrastructure Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc and the remaining bits and pieces to provide barebox i.MX6SL SoC support. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX6SL: import clock infrastructure from linuxAlexander Kurz2017-02-021-0/+329
| | | | | | | | | | | | | | Import i.MX6SL clock infrastructure from linux clk-imx6sl.c To save space, clocks beeing unlikely usefull for bootloader purposes (SSI, SPDIF, EXTERN_AUDIO) were not imported. Further, the fixup code from linux mainline commits a49e6c4b8204 ("ARM: imx: add common clock support for fixup mux") cbe7fc8aaeef ("ARM: imx: add common clock support for fixup div") was ignored for this commit. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX31 clk: add pll_ref_clk and MCU PLL bypass selectAlexander Kurz2017-01-261-5/+23
| | | | | | | | | | | The three MX31 PLL may be clocked from either CKIH or a frequency-multiplied derivate of CKIL generated by the Frequency Pre Multiplier FPM. Add the pll_ref_clk selection infrastructure and support for MCU PLL bypass to support clock switching and boards not clocked CKIH. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX7: Add missing USB clocksSascha Hauer2017-01-191-0/+3
| | | | | | The USB clocks are missing in the Kernel clock code. Add them here. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: Add clock support for i.MX7Juergen Borleis2017-01-193-0/+908
| | | | | Signed-off-by Juergen Borleis <jbe@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: Add clk-cpu supportSascha Hauer2017-01-193-0/+114
| | | | | | Taken from the kernel as of 4.10-rc3. Needed for i.MX7 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX: pllv3: Add support for the i.MX7 enet pllSascha Hauer2017-01-192-5/+19
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX: vf610: Ramp CPU clock to maximum frequencyAndrey Smirnov2017-01-121-2/+161
| | | | | | | | | | Mask ROM leaves the CPU running at 264Mhz, so configure the clock tree such that CPU runs at maximum supported frequency. Maximum supported frequncy is determined from speed grading burned into OCOTP fusebox by the vendor. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX: clk: Add IMX_PLLV3_SYS_VF610 subtypeAndrey Smirnov2017-01-122-0/+113
| | | | | | | | | | Add IMX_PLLV3_SYS_VF610 subtype to pllv3 code to be able to control and re-clock PLL1 and PLL2 on Vybrid SoC. This commit also introduces imx_clk_pllv3_locked which allows the user to create PLLv3 and specify how it should be polled for "locked" status (used in .set_rate callback) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/vybrid'Sascha Hauer2017-01-1223-1/+4951
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| * i.MX: Add VF610 clock tree initialization codeAndrey Smirnov2017-01-112-0/+447
| | | | | | | | | | | | | | Based on analogous code from Linux kernel Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Port imx_clk_mux_flags from LinuxAndrey Smirnov2017-01-111-0/+8
| | | | | | | | | | | | | | Port imx_clk_mux_flags from Linux, to simplify clock code porting. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Port imx_check_clocks()Andrey Smirnov2017-01-113-1/+26
| | | | | | | | | | | | | | Port imx_check_clocks() from Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Add IMX_PLLV3_USB_VF610 supportAndrey Smirnov2017-01-112-3/+7
| | | | | | | | | | | | | | Add IMX_PLLV3_USB_VF610 PLLv3 types support clk-pllv3.c Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Port imx_clk_gate2_cgr()Andrey Smirnov2017-01-112-7/+16
| | | | | | | | | | | | | | | | Update clk-gate2 code to be able to accept arbitrary 'cgr' value and introduce imx_clk_gate2_cgr() (Used by Vybrid clock tree) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: Move clk code from 'mach-imx' to 'drivers'Andrey Smirnov2017-01-1118-0/+3881
| | | | | | | | | | | | | | | | | | Move clk code from 'mach-imx' to 'drivers' to keep the code tree structure closer to that of analogous one from Linux kernel and, arguably although subjective, to keep 'mach-imx' less cluttered. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: Port of_clk_set_defaults()Andrey Smirnov2017-01-113-1/+151
|/ | | | | | | | Port of_clk_set_defautls() from Linux kernel in order to support DT configurations that require it (e. g. Vybrid). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/vybrid'Sascha Hauer2016-11-141-7/+82
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| * clk: Port clock dependency resolution codeAndrey Smirnov2016-11-141-7/+82
| | | | | | | | | | | | | | | | | | | | Port the clock dependency resolution algorithm utilized by Linux kernel's version of of_clk_init(), to allow for SoCs whose DT clock configuration reqires such behaviour for correct initialization (Vybrid is one such example). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: add clock command completionSascha Hauer2016-11-081-0/+22
|/ | | | | | This adds tab completion for the clk_* commands. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2016-09-131-3/+22
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| * clk: socfpga: add divider registers to the main pll outputsEnrico Jorns2016-08-181-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on kernel patch 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf by Dinh Nguyen <dinguyen@altera.com>. The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Note: The registers used for the div-reg property are not documented but set by the preloader. Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Add RK3288 clock driverWadim Egorov2016-08-262-1/+839
|/ | | | | | | | Add clk driver for RK3288 SoC. This driver comes from the Linux kernel. Based on kernel v4.4 Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: fix misleading indentingLucas Stach2016-07-071-2/+2
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: ath79: dts: sync clk stuff with linux v4.7-rc2Antony Pavlov2016-06-141-27/+6
| | | | | | | | | | | | | | | | | | | Please see these linux kernel ath79 commits: commit 1e6a3492e7bb12aa8ee26050ff6829c39ebaa152 Author: Antony Pavlov <antonynpavlov@gmail.com> Date: Thu Mar 17 06:34:17 2016 +0300 MIPS: dts: qca: introduce AR9331 devicetree commit 5ae5c452e3361612cd8182eb8bdfecf0ebf42288 Author: Antony Pavlov <antonynpavlov@gmail.com> Date: Thu Mar 17 06:34:18 2016 +0300 MIPS: ath79: update devicetree clock support for AR9331 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>