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* CLK: Add fractional divider clock support from Linux kernelAndrey Panov2015-03-052-1/+154
| | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* CLK: Add support for composite clock from Linux kernelAndrey Panov2015-03-052-1/+146
| | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: remove unnecessary mach/imx-regs.h includeSascha Hauer2015-01-052-2/+2
| | | | | | And replace the ones needed with the SoC specific header. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/tegra'Sascha Hauer2014-11-055-18/+380
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| * clk: tegra: don't enable UART clocks by defaultLucas Stach2014-11-043-14/+14
| | | | | | | | | | | | | | | | Now that we are registering a proper driver for the UARTs we no longer need to enable the clocks unconditionally. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra: slow down MSELECT to 102MHzLucas Stach2014-11-042-2/+2
| | | | | | | | | | | | | | | | Don't know where I got the 204MHZ previously, but 102MHz is the official supported maximum. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra124: add PCIe clocksLucas Stach2014-11-041-0/+35
| | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra124: add PLLE setup functionsLucas Stach2014-11-042-3/+177
| | | | | | | | | | | | | | | | This adds functions to bring up the new style Tegra114+ PLL_E. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra30: add PCIe clocksLucas Stach2014-10-081-0/+31
| | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra: add PLLE setup functionsLucas Stach2014-10-082-0/+122
| | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: gate: remove superfluous codeLucas Stach2014-10-211-10/+1
|/ | | | | | | This code didn't have any effect. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* resource: Let dev_request_mem_region return an error pointerSascha Hauer2014-09-168-12/+17
| | | | | | For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-divider: divider calculation in clk_set_rate needs DIV_ROUND_UPSascha Hauer2014-07-231-1/+1
| | | | | | | To make the resulting rate is always smaller than the desired rate, and not bigger. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: mvebu: fix Armada 370 TCLK frequenciesSebastian Hesselbarth2014-06-241-2/+2
| | | | | | | This fixes Armada 370 TCLK frequencies that are off by a factor of 10. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* clk: tegra: add Tegra124 driverLucas Stach2014-06-052-0/+350
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: don't bug out on zero PLL postdivLucas Stach2014-06-051-2/+0
| | | | | | | | As the real value is 2^p a input value of 0 is actually valid. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: allow variable sized muxesLucas Stach2014-06-051-2/+4
| | | | | | | | Tegra124 extended the mux by 1bit to allow for more PLL sources. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra20: register i2c clocksLucas Stach2014-05-151-0/+13
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra30: register i2c clocksLucas Stach2014-05-151-0/+16
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: allow to register clocks with 16 bit dividerLucas Stach2014-05-152-7/+25
| | | | | | | | Some peripherals have a double wide divider in front of them. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: remove device reset hackLucas Stach2014-05-151-18/+0
| | | | | | | | | Now that we have a proper reset controller, it isn't necessary anymore to keep the device reset hack coupled to the clock. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: reset UARTS from clock controllerLucas Stach2014-05-154-0/+15
| | | | | | | | | | The console devices are the only ones that can't use the reset controller properly, as they get registered from platform code. Reset those devices from the clock controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* reset: add tegra reset controllerLucas Stach2014-05-154-1/+149
| | | | | | | | Allows us to drop the hack in the clock controller and implement proper reset at device level. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/tegra'Sascha Hauer2014-05-054-94/+462
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/dts/tegra20-colibri.dtsi arch/arm/dts/tegra20-paz00.dts arch/arm/dts/tegra20.dtsi drivers/clk/tegra/clk-periph.c
| * clk: tegra: add Tegra3 driverLucas Stach2014-04-232-1/+367
| | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra: consider new T30 clock registersLucas Stach2014-04-231-5/+15
| | | | | | | | | | | | | | | | | | Tegra3 has some new clocks and resets. The new registers don't form a linear range with the old ones. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra20: convert to dt-binding definesLucas Stach2014-04-071-88/+80
| | | | | | | | | | | | | | | | Allows to make relationship between DT and driver more explicit and avoids duplication. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: add rockchip clock gate driverBeniamino Galvani2014-04-293-0/+88
| | | | | | | | | | Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: gate: add CLK_GATE_HIWORD_MASK flagBeniamino Galvani2014-04-291-5/+12
| | | | | | | | | | | | | | | | | | Clock gates having the CLK_GATE_HIWORD_MASK flag set use the upper 16 bits of the register as a "write enable" mask for the value in the lower 16 bits. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: gate: unify enable and disable functions handlingBeniamino Galvani2014-04-291-18/+15
| | | | | | | | | | | | | | To avoid code duplication and make easier to introduce new flags. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: gate: add flags argument to clock gate constructorBeniamino Galvani2014-04-294-10/+8
| | | | | | | | | | | | | | | | This adds a clk_gate_flags argument to clock gate creation functions to allow the introduction of new clock gate modifiers. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: fixed-factor: add DT init functionAntony Pavlov2014-04-291-0/+36
| | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: move of_clk_get_parent_name() to common clk codeAntony Pavlov2014-04-292-19/+20
| | | | | | | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | treewide: fix signedness mixups in printf format specifiersLucas Stach2014-04-231-1/+1
|/ | | | | | | | | This most likely doesn't fix any real bugs, but it's the right thing to do and reduces the noise level with static checkers. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mips'Sascha Hauer2014-04-042-0/+176
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| * clk: add Atheros AR933x driverAntony Pavlov2014-03-282-0/+174
| | | | | | | | | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Add parent round/set rate for mux and gateSascha Hauer2014-03-283-0/+24
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: clk-fixed-factor: add set_rate/round_rate callbacksSascha Hauer2014-03-281-0/+30
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: let clk-divider handle the table based divider aswellSascha Hauer2014-03-283-121/+37
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: clk-divider: sync with kernel codeSascha Hauer2014-03-281-30/+161
| | | | | | | | | | | | | | | | This updates the clk-divider to Kernel code, but without power-of-two divider support which we do not need yet. This also adds table based divider support to the divider. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: clk-divider: pass flags to initializersSascha Hauer2014-03-282-4/+6
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: clk-fixed-factor: pass flags to initializersSascha Hauer2014-03-284-4/+5
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: clk-gate: pass flags to initializersSascha Hauer2014-03-285-9/+10
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: clk-mux: pass clk flags from initializersSascha Hauer2014-03-283-5/+7
| | | | | | | | | | | | | | struct clk has a flags field, let the clk-mux initializers set this field. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: implement clk_round_rateSascha Hauer2014-03-281-0/+10
|/ | | | | | | Instead of returning just the current rate implement clk_round_rate properly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers/clk/clk-divider-table.c: Fix sparse warningAlexander Shiyan2014-02-171-1/+1
| | | | | | | drivers/clk/clk-divider-table.c:81:16: warning: symbol 'clk_divider_table_ops' was not declared. Should it be static? Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers/clk/clk-gate.c: Fix sparse warningAlexander Shiyan2014-02-171-1/+1
| | | | | | | drivers/clk/clk-gate.c:79:16: warning: symbol 'clk_gate_ops' was not declared. Should it be static? Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers/clk/clk-mux.c: Fix sparse warningAlexander Shiyan2014-02-171-1/+1
| | | | | | | drivers/clk/clk-mux.c:53:16: warning: symbol 'clk_mux_ops' was not declared. Should it be static? Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers/clk/clk-fixed-factor.c: Fix sparse warningAlexander Shiyan2014-02-171-1/+1
| | | | | | | drivers/clk/clk-fixed-factor.c:38:16: warning: symbol 'clk_fixed_factor_ops' was not declared. Should it be static? Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers/clk/clk-fixed.c: Fix sparse warningAlexander Shiyan2014-02-171-1/+1
| | | | | | | drivers/clk/clk-fixed.c:35:16: warning: symbol 'clk_fixed_ops' was not declared. Should it be static? Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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