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* Merge branch 'for-next/vybrid'Sascha Hauer2017-01-1223-1/+4951
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| * i.MX: Add VF610 clock tree initialization codeAndrey Smirnov2017-01-112-0/+447
| | | | | | | | | | | | | | Based on analogous code from Linux kernel Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Port imx_clk_mux_flags from LinuxAndrey Smirnov2017-01-111-0/+8
| | | | | | | | | | | | | | Port imx_clk_mux_flags from Linux, to simplify clock code porting. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Port imx_check_clocks()Andrey Smirnov2017-01-113-1/+26
| | | | | | | | | | | | | | Port imx_check_clocks() from Linux kernel. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Add IMX_PLLV3_USB_VF610 supportAndrey Smirnov2017-01-112-3/+7
| | | | | | | | | | | | | | Add IMX_PLLV3_USB_VF610 PLLv3 types support clk-pllv3.c Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: clk: Port imx_clk_gate2_cgr()Andrey Smirnov2017-01-112-7/+16
| | | | | | | | | | | | | | | | Update clk-gate2 code to be able to accept arbitrary 'cgr' value and introduce imx_clk_gate2_cgr() (Used by Vybrid clock tree) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * i.MX: Move clk code from 'mach-imx' to 'drivers'Andrey Smirnov2017-01-1118-0/+3881
| | | | | | | | | | | | | | | | | | Move clk code from 'mach-imx' to 'drivers' to keep the code tree structure closer to that of analogous one from Linux kernel and, arguably although subjective, to keep 'mach-imx' less cluttered. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: Port of_clk_set_defaults()Andrey Smirnov2017-01-113-1/+151
|/ | | | | | | | Port of_clk_set_defautls() from Linux kernel in order to support DT configurations that require it (e. g. Vybrid). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/vybrid'Sascha Hauer2016-11-141-7/+82
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| * clk: Port clock dependency resolution codeAndrey Smirnov2016-11-141-7/+82
| | | | | | | | | | | | | | | | | | | | Port the clock dependency resolution algorithm utilized by Linux kernel's version of of_clk_init(), to allow for SoCs whose DT clock configuration reqires such behaviour for correct initialization (Vybrid is one such example). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: add clock command completionSascha Hauer2016-11-081-0/+22
|/ | | | | | This adds tab completion for the clk_* commands. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/socfpga'Sascha Hauer2016-09-131-3/+22
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| * clk: socfpga: add divider registers to the main pll outputsEnrico Jorns2016-08-181-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is based on kernel patch 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf by Dinh Nguyen <dinguyen@altera.com>. The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Note: The registers used for the div-reg property are not documented but set by the preloader. Signed-off-by: Enrico Jorns <ejo@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Add RK3288 clock driverWadim Egorov2016-08-262-1/+839
|/ | | | | | | | Add clk driver for RK3288 SoC. This driver comes from the Linux kernel. Based on kernel v4.4 Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: fix misleading indentingLucas Stach2016-07-071-2/+2
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MIPS: ath79: dts: sync clk stuff with linux v4.7-rc2Antony Pavlov2016-06-141-27/+6
| | | | | | | | | | | | | | | | | | | Please see these linux kernel ath79 commits: commit 1e6a3492e7bb12aa8ee26050ff6829c39ebaa152 Author: Antony Pavlov <antonynpavlov@gmail.com> Date: Thu Mar 17 06:34:17 2016 +0300 MIPS: dts: qca: introduce AR9331 devicetree commit 5ae5c452e3361612cd8182eb8bdfecf0ebf42288 Author: Antony Pavlov <antonynpavlov@gmail.com> Date: Thu Mar 17 06:34:18 2016 +0300 MIPS: ath79: update devicetree clock support for AR9331 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: ar933x: fix copyright headerAntony Pavlov2016-06-141-2/+2
| | | | | Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* driver: replace dev_request_mem_region with dev_request_mem_resourceSascha Hauer2016-03-079-30/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region doesn't work properly one some SoCs on which PTR_ERR() values clash with valid return values from dev_request_mem_region. Replace them with dev_request_mem_resource where possible. This patch has been generated with the following semantic patch: // <smpl> @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { ... - return PTR_ERR(io); -} + return PTR_ERR(iores); +} +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) - return PTR_ERR(io); -} + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { - ret = PTR_ERR(io); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { + ret = PTR_ERR(iores); ... } +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ identifier func; @@ func(...) { <+... struct resource *iores; -struct resource *iores; ...+> } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* driver: Fix return check of dev_request_mem_regionSascha Hauer2016-02-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region returns an ERR_PTR, fix places which check for a NULL pointer instead. This patch has been generated with this semantic patch, written by me and improved by Andrey Smirnov: // <smpl> @@ expression e; expression e1; @@ e = dev_request_mem_region(...); ... -if (!e) - return e1; +if (IS_ERR(e)) + return PTR_ERR(e); @ rule1 @ expression e; @@ e = dev_request_mem_region(...); @@ expression rule1.e; identifier ret, label; constant errno; @@ if (!e) { ... ( - ret = -errno; + ret = PTR_ERR(e); ... goto label; | - return -errno; + return PTR_ERR(e); ) } @depends on rule1@ expression rule1.e; @@ - if (e == NULL) + if (IS_ERR(e)) { ... } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
* clk: mvebu: Add corediv clock driver for Armada 370/XPSebastian Hesselbarth2015-10-122-2/+264
| | | | | | | | | Newer Marvell MVEBU SoC like Armada 370/XP have an additional core clock divider for e.g. NAND clock. Add the corresponding driver based on the Linux driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: socfpga: don't register fixed clocksSteffen Trumtrar2015-08-191-12/+1
| | | | | | | | | | | | | | The fixed clocks are registered from devicetree. Therefore the code path is not needed, but would instead register the clocks twice, which leads to the error message: clk_register clk f2s_periph_ref_clk is already registered, skipping! of_clk_init: failed to init clock for /soc/clkmgr@ffd04000/clocks/f2s_periph_ref_clk: 1 clk_register clk osc1 is already registered, skipping! of_clk_init: failed to init clock for /soc/clkmgr@ffd04000/clocks/osc1: 1 Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: socfpga: fix dt binding supportSteffen Trumtrar2015-08-191-21/+52
| | | | | | | | Change the set_parent/get_parent functions for clock-gates to work with the Linux kernel DT bindings. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX28: Add PWM clk supportSascha Hauer2015-06-121-0/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: use 'const void *' for struct of_device_id.dataAntony Pavlov2015-04-301-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 2011 barebox' of_device_id struct uses unsigned long type for data field: struct of_device_id { char *compatible; unsigned long data; }; Almost always struct of_device_id.data field are used as pointer and need 'unsigned long' casting. E.g. see 'git grep -A 4 of_device_id drivers/' output: drivers/ata/sata-imx.c:static __maybe_unused struct of_device_id imx_sata_dt_ids[] = { drivers/ata/sata-imx.c- { drivers/ata/sata-imx.c- .compatible = "fsl,imx6q-ahci", drivers/ata/sata-imx.c- .data = (unsigned long)&data_imx6, drivers/ata/sata-imx.c- }, { Here is of_device_id struct in linux kernel v4.0: struct of_device_id { char name[32]; char type[32]; char compatible[128]; const void *data; }; Changing of_device_id.data type to 'const void *data' will increase barebox' linux kernel compatibility and decrease number of 'unsigned long' casts. Part of the patch was done using the 'coccinelle' tool with the following semantic patch: @rule1@ identifier dev; identifier type; identifier func; @@ func(...) { <... - dev_get_drvdata(dev, (unsigned long *)&type) + dev_get_drvdata(dev, (const void **)&type) ...> } @rule2@ identifier dev; identifier type; identifier func; identifier data; @@ func(...) { <... - dev_get_drvdata(dev, (unsigned long *)&type->data) + dev_get_drvdata(dev, (const void **)&type->data) ...> } Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: fractional-divider: fix build with CONFIG_MODULESLucas Stach2015-03-261-1/+1
| | | | | | | | | | | Fixes: error: 'clk_register_fractional_divider' undeclared here introduced with commit 22a0c31c9265 (CLK: Add fractional divider clock support from Linux kernel) Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-divider: fix _get_maxdiv for table based dividerSascha Hauer2015-03-121-0/+13
| | | | | | | The divider lacks the code for calculating the maximum divider for table based dividers. Add it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rockchip'Sascha Hauer2015-03-0913-93/+2443
|\ | | | | | | | | Conflicts: arch/arm/Kconfig
| * ARM: Rockchip: Update clk driver from Linux kernel for use with newer DTSAndrey Panov2015-03-057-87/+2096
| | | | | | | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * CLK: Check and do not allow to register clock twiceAndrey Panov2015-03-051-0/+10
| | | | | | | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * CLK: clk-divider: Respect CLK_DIVIDER_POWER_OF_TWO flagAndrey Panov2015-03-051-0/+9
| | | | | | | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * CLK: clk-divider: Introduce clk_divider_alloc() and *_free() routinesAndrey Panov2015-03-051-5/+22
| | | | | | | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * CLK: clk-divider: Respect CLK_DIVIDER_HIWORD_MASK flagAndrey Panov2015-03-051-0/+4
| | | | | | | | | | | | | | | | It is required for Rockchip SoCs where clock settings registers have write-enable mask in high word. Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * CLK: clk-mux: Respect CLK_MUX_HIWORD_MASK flagAndrey Panov2015-03-051-0/+3
| | | | | | | | | | | | | | | | It is required for Rockchip SoCs where clock settings registers have write-enable mask in high word. Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * CLK: Add fractional divider clock support from Linux kernelAndrey Panov2015-03-052-1/+154
| | | | | | | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * CLK: Add support for composite clock from Linux kernelAndrey Panov2015-03-052-1/+146
| | | | | | | | | | Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Treat NULL as dummy clocksSascha Hauer2015-03-051-0/+17
|/ | | | | | | | | NULL pointers should be treated as dummy clocks as done in the kernel. Using a not fully filled in clk * array for of_clk_add_provider may result in NULL clks. When these are passed into the clk framework we should not crash. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* drivers: remove unnecessary mach/imx-regs.h includeSascha Hauer2015-01-052-2/+2
| | | | | | And replace the ones needed with the SoC specific header. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/tegra'Sascha Hauer2014-11-055-18/+380
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| * clk: tegra: don't enable UART clocks by defaultLucas Stach2014-11-043-14/+14
| | | | | | | | | | | | | | | | Now that we are registering a proper driver for the UARTs we no longer need to enable the clocks unconditionally. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra: slow down MSELECT to 102MHzLucas Stach2014-11-042-2/+2
| | | | | | | | | | | | | | | | Don't know where I got the 204MHZ previously, but 102MHz is the official supported maximum. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra124: add PCIe clocksLucas Stach2014-11-041-0/+35
| | | | | | | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra124: add PLLE setup functionsLucas Stach2014-11-042-3/+177
| | | | | | | | | | | | | | | | This adds functions to bring up the new style Tegra114+ PLL_E. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra30: add PCIe clocksLucas Stach2014-10-081-0/+31
| | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: tegra: add PLLE setup functionsLucas Stach2014-10-082-0/+122
| | | | | | | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: gate: remove superfluous codeLucas Stach2014-10-211-10/+1
|/ | | | | | | This code didn't have any effect. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* resource: Let dev_request_mem_region return an error pointerSascha Hauer2014-09-168-12/+17
| | | | | | For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: clk-divider: divider calculation in clk_set_rate needs DIV_ROUND_UPSascha Hauer2014-07-231-1/+1
| | | | | | | To make the resulting rate is always smaller than the desired rate, and not bigger. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: mvebu: fix Armada 370 TCLK frequenciesSebastian Hesselbarth2014-06-241-2/+2
| | | | | | | This fixes Armada 370 TCLK frequencies that are off by a factor of 10. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* clk: tegra: add Tegra124 driverLucas Stach2014-06-052-0/+350
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: tegra: don't bug out on zero PLL postdivLucas Stach2014-06-051-2/+0
| | | | | | | | As the real value is 2^p a input value of 0 is actually valid. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-28 17:40:40 +0000