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* clk: i.MX6qp: Fix location of the enfc_sel muxSascha Hauer2019-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | On the i.MX6qp the enfc_sel mux is at bits 15-17, not on 16-17. Fix this. During clock tree initialization we reparented the enfc_sel to: clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]); This resulted in a register setting 0b110 for the enfc_sel mux which is reserved. Apparently this reserved setting resulted in the enfc clock being driven from pll3_pfd3_454m. This means our enfc clock was the factor 454/396 too high. With b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK") we happened to disable pll3_pfd3_454m during init, so with this commit NAND stopped working entirely on i.MX6qp. Both issues are fixed with this patch Fixes: b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK") Fixes: 92fd61d12723 ("clk: i.MX6: Fix enfc_sel for i.MX6dqp") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: zynqmp: rename driver specific CLK_MUX_READ_ONLYMichael Tretter2019-09-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Since commit c7cc27d006cc (clk: mux: Support CLK_MUX_READ_ONLY flag) Barebox defines the CLK_MUX_READ_ONLY flag like Linux. The ZynqMP clock driver used the flag before, because this flag is used to convey this information from the PMU firmware to the Linux driver. However, the flags of the common clock framework and the flag of the protocol between PMU firmware and the ZynqMP clock driver should be handled separately. Therefore, add a driver specific prefix to the flag definition in the ZynqMP driver. Fixes the warning drivers/clk/zynqmp/clk-mux-zynqmp.c:18:0: warning: "CLK_MUX_READ_ONLY" redefined In file included from drivers/clk/zynqmp/clk-mux-zynqmp.c:13:0: include/linux/clk.h:350:0: note: this is the location of the previous definition Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: define an enum for ldb mux inputsAhmad Fatoum2019-08-051-15/+24
| | | | | | | | | | | | | | For better readability should this code be reviewed in future, replace the hardcoded input numbers with an enum. This is just a cosmetic change and was verified to not affect clk-imx6.o. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: Fix procedure to switch the parent of LDB_DI_CLKFabio Estevam2019-08-051-3/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. The glitchy muxes are then registered as read-only. The clock parent can be selected using the assigned-clocks and assigned-clock-parents properties of the ccm device tree node: &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; The issue is explained in detail in EB821 ("LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines") [1]. [1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com> Tested-by Joshua Clayton <stillcompiling@gmail.com> Tested-by: Charles Kang <Charles.Kang@advantech.com.tw> Signed-off-by: Shawn Guo <shawnguo@kernel.org> [afa: reviewed for barebox] Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> [afa: ported to barebox from Linux commit 5d283b0838] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-onlyPhilipp Zabel2019-08-052-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Kernel commit 03d576f202 ("clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only"): | Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk | tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to | enter the ldb_di_ipu_div divider. If the divider gets locked up, no | ldb_di[x]_clk is generated, and the LVDS display will hang when the | ipu_di_clk is sourced from ldb_di_clk. | | To fix the problem, both the new and current parent of the ldb_di_clk | should be disabled before the switch. As this can not be guaranteed by | the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. | A workaround to set the muxes once during boot could be added to the | kernel or bootloader. | | Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> | Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> | Signed-off-by: Shawn Guo <shawnguo@kernel.org> [afa: reviewed for barebox] Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> [afa: ported from Linux kernel commit 03d576f202] [afa: added exception for i.MX6QP, see kernel commit f4a0a6c309] [afa: added cpu_has_err009219 helper function] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: remove quirky clk_set_parent(LDB_diN_sel, pll5_video_div)Ahmad Fatoum2019-08-051-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox has inherited the clk_set_parent(ldb_diN_sel, pll5_video_div) from upstream kernel commit 32f3b8da22 ("ARM i.MX6q: set the LDB serial clock parent to the video PLL"), where it was enabled for all i.MX6Q revisions after 1.0. It was applied whenever CONFIG_DRIVER_VIDEO_IMX_IPUV3 was defined. The kernel removed this reparenting again as a preventive measure against ERR009219 in 03d576f202 ("clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only"). In barebox, the reparenting remains and is done for all i.MX6 SoCs with a revision > 1.0. On all of them, except for the QuadPlus and the DualPlus, this reparenting may glitch the LDB so that it permanently locks up. By removing the reparenting in this commit, producing this glitch is avoided. The device tree[1] can elect to reinstate the reparenting: &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; Follow-up patches will explicitly check for this and do reparenting defined this way in a glitch-free manner. As of v2019.07.0, following mainline boards are potentially broken by this (i.e. they're supported by barebox, are in the list above, had a LDB enabled and might be defining CONFIG_DRIVER_VIDEO_IMX_IPUV3): - imx6qdl-zii-rdu2.dtsi - imx6qdl-udoo.dtsi - imx6qdl-mba6x.dtsi - imx6q-var-custom.dts - imx6q-guf-santaro.dts - imx6q-embedsky-e9.dtsi [1]: If barebox is configured to show a boot splash screen, this snippet should exist in the barebox device tree. If barebox acts on it, the kernel will show following warning: ccm: ldb_di0_sel already changed from reset value: 0 ccm: ldb_di1_sel already changed from reset value: 0 This warning is safe to ignore. Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Raphael Poggi <poggi.raph@gmail.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podfPhilipp Zabel2019-08-051-0/+16
| | | | | | | | | | | | | | | | | | | | MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never succeed. Disable the handshake mechanism to allow changing the frequency of mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI clock. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> [afa: reviewed for barebox] Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> [afa: ported to barebox from Linux commit f13abeff2c] [afa: moved call site to where it would've been moved in following commit] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: fix use of cpu_is_mx6* before they are initializedAhmad Fatoum2019-08-051-6/+5
| | | | | | | | | | | | | | | | | | | | | The cpu_is_mx6* macros rely on __imx_cpu_type, which is initialized dependent on device tree compatible at "postcore" init-level imx_init. The imx6q-ccm driver, which uses the cpu_is_mx6* macros, is registered at "core" init-level, however. This results on the macro always returning false. Fix this by using the cpu_mx6_is_mx6* family of macros instead. These already require that that CPU is a MX6, which is safe because the the driver only matches against "fsl,imx6q-ccm". Only exception is the video5 pll reparenting. Here we will just maintain the old behavior as we will drop the if clause in a following commit anyway. Reported-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: divider: export clk_div_mask() helperMarcin Niestroj2019-07-041-9/+7
| | | | | | | | | | | | | | | | | commit e6d3cc7b1fac3d7f1313faf8ac9b23830113e3ec Linux upstream. clk: divider: export clk_div_mask() helper Export clk_div_mask() in clk-provider header so every clock providers derived from the generic clock divider may share the definition instead of redefining it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: divider: Make generic for usage elsewhereMarcin Niestroj2019-07-021-45/+71
| | | | | | | | | | | | | | | | | | commit bca9690b942654f668ffb5124b2bbd0ba0f007bb Linux upstream adjusted to current Barebox codebase. clk: divider: Make generic for usage elsewhere Some devices don't use mmio to interact with dividers. Split out the logic from the register read/write parts so that we can reuse the division logic elsewhere. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: divider: Fix best div calculation for power-of-two and table dividersMarcin Niestroj2019-07-021-1/+35
| | | | | | | | | | | | | | | | | | commit dd23c2cd38da2c64af381b19795d2c4f115e8ecb Linux upstream. clk: divider: Fix best div calculation for power-of-two and table dividers The divider returned by clk_divider_bestdiv() is likely to be invalid in case of power-of-two and table dividers when CLK_SET_RATE_PARENT flag isn't set. Fixes boot on STiH416 platform. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: trivial merge conflict & updated changelog] Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: divider: Remove unused variable in clk_divider_recalc_rateMarcin Niestroj2019-07-021-3/+1
| | | | | | | | | | commit "clk: add divider_recalc_rate helper" reworked clk_divider_recalc_rate() function and as part of that left one variable assignment, which is not used later. Fixes: e27c0b64db01 ("clk: add divider_recalc_rate helper") Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2019-06-111-1/+1
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| * clk: imx: vf610: correct __iomem 'qualifier' placementAhmad Fatoum2019-05-241-1/+1
| | | | | | | | | | | | | | | | __iomem applies to the IOMEM() pointee, not to the auto pointer that points at it. Move the annotation to correct this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: fix warning about missing const-safetyAhmad Fatoum2019-05-272-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | compiling clk-main.c and clk-generated.c results in: warning: passing argument 1 of 'memcpy' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] memcpy(clkmain->clk.parent_names, parent_names, parents_array_size); ~~~~~~~~~~~~^~~~~~~~~~~~~ Avoid this by replacing the xzalloc+memcpy pair with xmemdup. Zero-initialization of the buffer isn't necessary, because memcpy spans the whole buffer. Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: delete dead i2s/audio codeAhmad Fatoum2019-05-242-112/+0
| | | | | | | | | | | | | | | | | | They aren't used anywhere, thus drop them. Suggested-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: fix compilation errors in sama5d2.cAhmad Fatoum2019-05-242-63/+6
|/ | | | | | | | | | | | | | | | | sama5d2.c was added alongside the update to the remaining clk drivers to support the new upstream device tree bindings, but wasn't wired in anywhere. To prepare for usage in future sama5d2 support, fix compilation errors related to absence of locks and unavailability of audio/i2s clock/pll handling. With this change, there are no users for the few definition-less at91 audio/i2s registration function declarations. So remove those as well. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: vf610: improve handling case that cpu frequency can't be changedHeiner Kallweit2019-04-291-15/+18
| | | | | | | | | | | | | | | | | Currently we get a nasty error message if the cpu clock can't be changed: DDRC is clocked by PLL1, can't switch CPU clockinitcall vf610_switch_cpu_clock+0x1/0x198 failed: Invalid argument So let's do the following: - factor out the check from vf610_switch_cpu_clock_to_500mhz() and vf610_switch_cpu_clock_to_400mhz - if clock can't be changed, don't treat it as an error - don't call clock notifier chain if clock can't be changed - add trailing newline to the warning message Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX25: Add some more clocksSteffen Trumtrar2019-04-121-1/+6
| | | | | | | | | | Add some clocks needed for: - RNGB - SCC - Dryice RTC Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: socfpga: fix compiler warnings for Cyclone5Ian Abbott2019-04-101-3/+3
| | | | | | | | | | | | | | | When building for Cyclone5 SoCFPGA, the socfpga_a10_pll_init(), socfpga_a10_perith_init() and socfpga_a10_gate_init() functions are defined as dummy functions returning ERR_PTR(-ENOSYS). They are defined with external linkage. With '-Wmissing-prototypes' GCC warns about externally linked function definitions with no preceding prototype. Define them as 'static inline' to avoid the compiler warnings. (Note: Arria10 uses non-dummy versions of these functions declared 'extern' but defined elsewhere.) Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynqmp'Sascha Hauer2019-04-098-0/+1162
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| * clk: add ZynqMP clock driverMichael Tretter2019-03-188-0/+1162
| | | | | | | | | | | | | | | | | | | | | | | | The ZynqMP has a platform management unit (PMU) that is responsible for managing the clocks. Therefore, the clock driver uses the firmware driver to control the clocks. The Barebox driver is based on the Linux driver, but contains deviations to make the driver more readable and more consistent. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/warnings'Sascha Hauer2019-04-093-4/+4
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| * | treewide: Make locally used functions staticSascha Hauer2019-03-183-4/+4
| |/ | | | | | | | | | | | | Many functions are only used locally but still are globally visible. Make these function static. Avoids warnings generated with -Wmissing-prototypes Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/stm32'Sascha Hauer2019-04-0916-56/+2069
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| * | ARM: stm32mp1: Add clk driverSascha Hauer2019-03-112-0/+1989
| | | | | | | | | | | | | | | | | | | | | Taken from Linux v5.0-rc2. Mostly as-is, only adopted to the differences between the Linux and barebox clk API. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: mux: Support CLK_SET_RATE_NO_REPARENT flagSascha Hauer2019-03-112-4/+0
| | | | | | | | | | | | | | | | | | | | | Since barebox doesn't do reparenting on rate changes we only have to define the flag. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: mux: Support CLK_MUX_READ_ONLY flagSascha Hauer2019-03-111-0/+7
| | | | | | | | | | | | | | | | | | Support readonly dividers using the CLK_MUX_READ_ONLY flag. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: mux: Support mux specific flagsSascha Hauer2019-03-116-24/+27
| | | | | | | | | | | | | | | | | | | | | We'll need mux specific flags in the future, so add a parameter to the mux initialization functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: divider: Support CLK_DIVIDER_READ_ONLY flagSascha Hauer2019-03-113-2/+7
| | | | | | | | | | | | | | | | | | To support a readonly divider add the CLK_DIVIDER_READ_ONLY flag. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: divider: pass divider flagsSascha Hauer2019-03-114-21/+29
| | | | | | | | | | | | | | | | | | | | | The generic clk divider needs clock flags and divider flags. Fix prototypes to take both as separate arguments. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: Support CLK_IS_CRITICAL flagSascha Hauer2019-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | | Support CLK_IS_CRITICAL flag. Simply do not disable the clock even when the enable count is zero. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: Make CLK_IGNORE_UNUSED genericSascha Hauer2019-03-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | barebox will never disable unused clocks, so add CLK_IGNORE_UNUSED as a no-op flag. With this we can keep the changes to the imported kernel code smaller. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: export clk_gate_is_enabled()Sascha Hauer2019-03-111-1/+1
| | | | | | | | | | | | | | | | | | Will be needed by stm32 clk support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: parent_names should be constSascha Hauer2019-03-112-3/+3
| | | | | | | | | | | | | | | | | | | | | Not only the array of pointers should be const, but also the strings they point to. Add missing const. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: clk-composite: return parent_rate if no rate clkSascha Hauer2019-03-111-1/+4
| |/ | | | | | | | | | | | | When a composite clock has no rate clock then it should output the parents rate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / clk: Add Layerscape clk supportSascha Hauer2019-03-132-0/+666
|/ | | | | | | | | | This adds support for the clock controller found on Layerscape SoCs. This is mostly an adoption of the corresponding Linux driver. This is tested on the LS1046a SoC. Other ARM based Layerscape SoCs should work aswell, support for the PowerPC based SoCs has been removed. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx8-usb'Sascha Hauer2019-03-073-6/+104
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| * clk: Import a subset of clk_bulk API from LinuxAndrey Smirnov2019-02-222-1/+104
| | | | | | | | | | | | | | | | Import a subset of clk_bulk API from Linux to support porting kernel code that uses it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: Drop separate definitions of clk_put()Andrey Smirnov2019-02-221-5/+0
| | | | | | | | | | | | | | | | | | Regardless of the value of CONFIG_HAVE_CLK, clk_put() implementation is always a no-op. Move the definition to linux/clk.h and drop the rest of the code implementing it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: update to PMC bindingsSam Ravnborg2019-02-2516-970/+567
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on kernel 5.0-rc6 update at91 clk support to match the new PMC bindings. Manually added all changes done in the kernel from 4.9-rc3 to 5.0-rc6. New drivers required was added as seperate commits. This includes dt-compat code required to support at91sam5d3, as this is not yet ported to use the new PMC bindings. clk-programmable saw some extra changes - it had never been bulit. It is used only by at91sama5d2 - and barebox has no board support for this cpu (yet). The CONFIG_SOC symbols is used to select the relevant drivers. CONFIG_SOC_SAM9 selects several drivers, and in the future this can be split to keep the image size down. In the kernel CLK_OF_DECLARE_DRIVER() can be used for a two step init. In barebox this is a simple one step init. It was added to have less differences between the kernel and the barebox versions of the drivers. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: add dt-compat to PMC bindingsAhmad Fatoum2019-02-251-0/+961
| | | | | | | | | | | | | | | | | | | | | | As the sama5d3 based microchip-ksz9477-evb board still uses the old bindings, the dt-compat.c code is ported as well. This can be removed when all in-kernel at91 boards have been ported to the new bindings. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: add sama5d4Sam Ravnborg2019-02-251-0/+270
| | | | | | | | | | | | | | | | | | | | | | | | Add sama5d4 as part of supporting the PMC bindings for ARM at91. The file will be wired into the build in a follow-up patch. The file is a copy from kernel 5.0-rc6 modified to build with barebox. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: add sama5d2Sam Ravnborg2019-02-251-0/+342
| | | | | | | | | | | | | | | | | | | | | | | | Add sama5d2 as part of supporting the PMC bindings for ARM at91. The file will be wired into the build in a follow-up patch. The file is a copy from kernel 5.0-rc6 modified to build with barebox. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: add at91sam9x5Sam Ravnborg2019-02-251-0/+315
| | | | | | | | | | | | | | | | | | | | | | | | Add at91sam9x5 as part of supporting the PMC bindings for ARM at91. The file will be wired into the build in a follow-up patch. The file is a copy from kernel 5.0-rc6 modified to build with barebox. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: add at91sam9rlSam Ravnborg2019-02-251-0/+177
| | | | | | | | | | | | | | | | | | | | | | | | Add at91sam9rl as part of supporting the PMC bindings for ARM at91. The file will be wired into the build in a follow-up patch. The file is a copy from kernel 5.0-rc6 modified to build with barebox. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: at91: add at91sam9260Sam Ravnborg2019-02-251-0/+497
|/ | | | | | | | | | | | Add at91sam9260 as part of supporting the PMC bindings for ARM at91. The file will be wired into the build in a follow-up patch. The file is a copy from kernel 5.0-rc6 modified to build with barebox. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Tested-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* treewide: Remove trailing whitespaces and tabsAlexander Shiyan2019-01-211-1/+1
| | | | | | | Just a cleanup over barebox tree Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: sync imx8mq clock driver with upstream kernelLucas Stach2019-01-152-277/+265
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: add imx8mq composite clockLucas Stach2019-01-153-0/+184
| | | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-19 20:00:02 +0000