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* Merge branch 'for-next/misc'Sascha Hauer2020-07-271-3/+1
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| * treewide: Convert files covered by ARM copyright to SPDXUwe Kleine-König2020-07-141-3/+1
| | | | | | | | | | | | | | | | | | | | According to Marc Zyngier, former employee at ARM, the company owns the copyright for code created by its employees. Convert accordingly to SPDX with the usual rearrangements. Also dropped Marc's email address which doesn't work any more. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2020-07-272-0/+722
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| * | clk: imx: Add imx8mp clk driverOleksij Rempel2020-07-142-0/+722
| |/ | | | | | | | | | | This adds clock support for the i.MX8MP, taken from Linux-5.7. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
* | Merge branch 'for-next/dts'Sascha Hauer2020-07-2715-791/+1020
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| * | clk: at91: remove now-duplicate crutch #definesAhmad Fatoum2020-07-051-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | As the code comment describes, these #defines were only needed temporarily till dts/ is synced vs Linux v5.8-rc1. This is now the case, so drop them again. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: at91: remove no-longer needed dt-compat codeAhmad Fatoum2020-07-052-732/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dt-compat.c implemented bindings for following compatibles: atmel,at91rm9200-clk-main-osc atmel,at91sam9x5-clk-main-rc-osc atmel,at91rm9200-clk-main atmel,at91sam9x5-clk-main atmel,at91rm9200-clk-master atmel,at91sam9x5-clk-master atmel,at91rm9200-clk-peripheral atmel,at91sam9x5-clk-peripheral atmel,at91rm9200-clk-pll atmel,sama5d3-clk-pll atmel,at91sam9x5-clk-plldiv atmel,at91rm9200-clk-programmable atmel,at91sam9g45-clk-programmable atmel,at91sam9x5-clk-programmable atmel,at91sam9x5-clk-smd atmel,at91rm9200-clk-system atmel,at91sam9x5-clk-usb atmel,at91sam9n12-clk-usb atmel,at91rm9200-clk-usb atmel,at91sam9x5-clk-utmi With the recent v5.8-rc1 sync, we no longer have any device trees in the barebox repository that use these. Unlike Linux, we don't need to support probing from old device trees, so drop the now unused code. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | clk: at91: sync with Linux v5.8-rc1Ahmad Fatoum2020-07-0514-63/+1025
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This ports over a couple of changes that accrued upstream between v5.6, when we last synchronized, and v5.8-rc1: 5bf7f4a24938 clk: at91: sam9x60: Don't use audio PLL b0ecf1c6c6e8 clk: at91: usb: continue if clk_hw_round_rate() return zero 43b203d32b77 clk: at91: sam9x60: fix usb clock parents d7a83d67a169 clk: at91: usb: use proper usbs_mask 9962fb0d1995 clk: at91: usb: introduce num_parents in driver's structure 12dc8d3be9d8 clk: at91: add at91sam9g45 pmc driver 0969b242f7b8 clk: at91: add sama5d3 pmc driver 143e04dab6b4 clk: at91: add at91sam9n12 pmc driver 02ff48e4d7f7 clk: at91: add at91rm9200 pmc driver 99e107439eea clk: at91: Add peripheral clock for PTC f6363c437dc6 clk: at91: pmc: do not continue if compatible not located 7425f246f725 clk: at91: optimize pmc data allocation 99767cd4406f clk: at91: allow setting PCKx parent via DT 03a1ee1dad0e clk: at91: allow setting all PMC clock parents via DT Besides fixes, mostly around sam9x60, this adds support for the new a91 device tree clock bindings that were extended to the sama5d3 in v5.8-rc1. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: sync of_clk_get_parent_name with upstreamAhmad Fatoum2020-06-231-5/+44
|/ | | | | | | | | | | | | Upstream of_clk_get_parent_name only resorts to node name as a fallback. Instead, it uses the name supplied for registered clocks whenever possible. On the sama5d2, this results in sckc@f8048050 and slowck, respectively. So far, sckc@f8048050 in the parents array couldn't be matched with any existing clock, leading to an inaccurate clock tree. Port over the v5.8-rc1 state of the function to fix this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: mxs: Use device tree provided clock lookupsSascha Hauer2020-05-061-19/+26
| | | | | | | | When probing from the device tree use the device tree provided clock lookups. So far we only used the clock lookups based on the physical base address of the device, but these should go sooner or later. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk imx28: Add USB clocksSascha Hauer2020-05-061-0/+13
| | | | | | | The USB clocks are missing, add them to make USB work as part of the i.MX chipidea driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: mxs: Fix clock numberingSascha Hauer2020-05-061-2/+2
| | | | | | | | The device tree clock lookups use the position in the clks array, hence they must match. fec_sleep is a barebox specific clock and is in between other clocks. Put the clock at the end of the array. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: mxs: Do not enable enet_out clockSascha Hauer2020-05-061-1/+0
| | | | | | | | | | | | | | The enet_out clock gate is wrongly abstracted. The bit it is controlling is not just a bit to enable the clock, it also controls the direction of the ethernet reference clock. When the bit is cleared, the ethernet reference clock must be fed into the SoC from an external oscillator; when it's set then the ethernet reference clock is generated internally. The correct setting depends on the board, so we must not set the bit unconditionally during probe of the clock driver. Whether or not the clock is enabled can be selected by the board by removing the clock from the FEC in its dts. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: sckc: fix off-by-1000 in udelay()Ahmad Fatoum2020-04-151-1/+1
| | | | | | | | SECOND is the number of nanoseconds in a second, but we need the number of microseconds for use in udelay. Use USEC_PER_SEC. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: port Linux v5.6 SAM9X60 (new ARM926EJ-S) clock supportAhmad Fatoum2020-04-1517-214/+1085
| | | | | | | | | | | | During a bug hunt that ultimately turned out unrelated to the state of the barebox at91 clk driver, I synchronized its state with Linux v5.6. Bug fixes and clean up to minimize the diff were split out in separate prior commits. This last commit imports the rest, which is basically support for Microchip's new ARM926EJ-S SoC, the SAM9x60. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: add sama5d2 audio PLL supportAhmad Fatoum2020-04-157-5/+669
| | | | | | | | | | | | | | | | | Commit 7310b976 ("clk: at91: fix compilation errors in sama5d2.c") and follow-up commit ca3077068c ("clk: at91: delete dead i2s/audio code") had deleted the i2s/audio clock related parts of the upstream driver. This was mostly due to unwillingness on my part to understand the code enough for porting them and because I deemed them unnecessary to support in barebox. The former has changed and the latter is not totally true as audio PLL derived clocks may be muxed as inputs for programmable and generated clocks. Port them over and mimize the diff to upstream. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: allow 24 Mhz clock as input for PLLEugen Hristev2020-04-151-1/+1
| | | | | | | | | | | | | | The PLL input range needs to be able to allow 24 Mhz crystal as input Update the range accordingly in plla characteristics struct Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> [afa: ported to barebox from Linux commit 81a6b601f9f49] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: Mark struct clk_range as constStephen Boyd2020-04-156-12/+12
| | | | | | | | | | | It's just some static data that doesn't get changed after being used. Mark it const everywhere. Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> [afa: ported to barebox from Linux commit 7b4c162e03d47e0] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: add __init marker where appropriateAhmad Fatoum2020-04-1512-38/+38
| | | | | | | | While redundant in barebox, it makes our diff to the upstream driver smaller when synchronizing, so add it back. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: compile dt-compat for all platforms that require itAhmad Fatoum2020-04-151-6/+4
| | | | | | | | | | | | We have so far compiled in dt-compat only for CONFIG_SOC_SAMA5D3, but we require it for device tree support of CONFIG_SOC_AT91SAM9 as well. Fix this. While at it move around the obj- rules a bit to minimize the diff to upstream. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: delete no-longer required DT compat codeAhmad Fatoum2020-04-151-133/+0
| | | | | | | | | | | | | | | | | Unlike Linux, we don't require barebox drivers to support old device tree bindings. Following device tree compatibles are no longer present in barebox latest import of dts/: * atmel,sama5d2-clk-generated * atmel,sama5d4-clk-h32mx * atmel,at91sam9g45-clk-pll * atmel,at91sam9g20-clk-pllb * atmel,at91sam9260-clk-slow Drop their compat code. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: fix possible deadlockAlexandre Belloni2020-04-156-6/+6
| | | | | | | | | | | | | | | | | | | Lockdep warns about a possible circular locking dependency because using syscon_node_to_regmap() will make the created regmap get and enable the first clock it can parse from the device tree. This clock is not needed to access the registers and should not be enabled at that time. Use the recently introduced device_node_to_regmap to solve that as it looks up the regmap in the same list but doesn't care about the clocks. Reported-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20191128102531.817549-1-alexandre.belloni@bootlin.com Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Stephen Boyd <sboyd@kernel.org> [afa: ported to barebox from from Linux commit 6956eb33abb5dea] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: at91: fix masterck nameAlexandre Belloni2020-04-153-4/+4
| | | | | | | | | | | | | | | | The master clock is actually named masterck earlier in the driver. Having "mck" in the parent list means that it can never be selected. Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver") Fixes: a2038077de9a ("clk: at91: add sama5d2 PMC driver") Fixes: 084b696bb509 ("clk: at91: add sama5d4 pmc driver") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by: Stephen Boyd <sboyd@kernel.org> [afa: ported to barebox from Linux commit 65a91e2e597dea] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: migrate to SPDX-License-Identifier useAhmad Fatoum2020-04-15106-751/+110
| | | | | | | | | | | | Some of these are a product of source sync with Linux, the other were done with macro assistance by searching for /later/, deleting license text, adding appropriate SPDX-License-Identifier and manual post-review. Devices without a license indicated where assumed GPL-2.0-only according with the project's license. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: implement clk_register_fixed_rateAhmad Fatoum2020-04-151-1/+15
| | | | | | | | | | | | | We lack a way to instantiate a fixed clock while specifying a parent. This is used in the at91 clock code sync with upstream in a later commit, so prepare by porting clk_register_fixed_rate. It's based on the Linux commit of the same name with the difference that it doesn't use (and thus doesn't require) a struct device_d * as first parameter. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/imx'Sascha Hauer2020-03-184-0/+1073
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| * clk: imx: Add imx8mm clk driverSascha Hauer2020-02-192-0/+578
| | | | | | | | | | | | This adds clock support for the i.MX8MM, taken from Linux-5.5. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: imx: Add imx8m_clk_composite_criticalSascha Hauer2020-02-191-0/+3
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: imx: Add pll14xx supportSascha Hauer2020-02-193-0/+492
| | | | | | | | | | | | | | | | This adds support for the pll14xx found on i.MX8MM devices. This is taken from the Kernel as of v5.5. Since we'll need some early setup for the PLL a PBL hook is added to be called from lowlevel code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: print more consistent clock statesSascha Hauer2020-02-251-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In clk_dump we only print the state of clk_is_enabled(). Depending on the clock this can mean different things. When the clock provides an is_enabled() callback it will print its result, so the enabled state matches the hardware state of that clock, but doesn't necessarily mean its parents are enabled. If a clock does not provide an is_enabled() callback then we rely on our internal enable_count tracker. Change this to always print the hardware state of the current clock. It can be: - disabled: The clock is disabled (as provided by is_enabled()) - enabled: The clock is enabled (as provided by is_enabled()) - always enabled: The clock can't be disabled (no is_enabled callback and can't be enabled/disabled) - unknown: no is_enabled callback but can be enabled/disabled Additionally we print the enable_count variable, so from enable_count != 0 we can know that barebox has enabled the clock. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: Do not let the enable count of critical clocks go below 1Sascha Hauer2020-02-251-3/+5
| | | | | | | | | | | | | | | | The enable count of critical clocks may not drop below 1. Otherwise the new parent during a reparenting of a critical clock will not be enabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: initially enable critical clocksSascha Hauer2020-02-251-0/+3
|/ | | | | | | | | Critical clocks have to be enabled initially. We have to do this not only to enable the clock itself, but also to make sure its parents stay enabled and also to correctly enable the new parents during reparenting of the clock. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX1: make locally used function staticSascha Hauer2020-02-181-1/+1
| | | | | | mx1_clocks_init() is only used in one file, make it static. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: zynq: add QSPI reference clockLucas Stach2019-12-201-0/+3
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/zynq'Sascha Hauer2019-12-103-0/+507
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| * clk: zynq: remove clkdevsLucas Stach2019-11-111-9/+0
| | | | | | | | | | | | | | | | They aren't needed anymore, as all the Zynq devices now use a DT based clock lookup. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: zynq: partially sync with LinuxLucas Stach2019-11-111-16/+71
| | | | | | | | | | | | | | | | | | | | Sync the clock enum with the clocks used by Linux and the DT binding. Implement AMBA bus clocks and SPI and SDIO peripheral clocks and register a DT clock controller, so the clocks can be looked up by DT handle. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: zynq: fix up address from DTLucas Stach2019-11-111-1/+23
| | | | | | | | | | | | | | | | | | | | The upstream Zynq 7000 DT describes the SLCR child devices physical address as an offset within the SLCR. The driver thus needs to add the SLCR base offset to the address before trying to map the MMIO region. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: zynq: improve PLL enable handlingLucas Stach2019-11-111-1/+12
| | | | | | | | | | | | | | | | | | | | | | Ensure that both the powerdown and reset bits are cleared when the PLL gets enabled, as any of those set would prevent the PLL from working. Also add a status readback function, so the real status of the PLL is reflected in the Barebox clock state. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * clk: zynq: use base address of clock controllerLucas Stach2019-11-111-15/+15
| | | | | | | | | | | | | | | | | | The clock controller is a subregion of the SLCR, use the real base of this region for mapping the registers. This will allow to switch to DT based probing later. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: zynq: move clock controller driver to drivers/clkLucas Stach2019-11-113-0/+428
| | | | | | | | | | | | | | No functional change, just adjusting the Zynq code to common practise. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | clk: i.MX6ul: Disable GPMI_IO clk before reparentingSascha Hauer2019-12-091-0/+3
|/ | | | | | | | | | | Before reparenting the ENFC_SEL mux we have to make sure the GPMI_IO clk is disabled as recommended in the reference manual. Otherwise glitches may occur on the GPMI clk which result in a later NAND failure: MXS: Timeout resetting block via register 0x01806000 mxs_nand 1806000.gpmi-nand@1806000.of: probe failed: Connection timed out Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: i.MX6qp: Fix location of the enfc_sel muxSascha Hauer2019-09-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | On the i.MX6qp the enfc_sel mux is at bits 15-17, not on 16-17. Fix this. During clock tree initialization we reparented the enfc_sel to: clk_set_parent(clks[IMX6QDL_CLK_ENFC_SEL], clks[IMX6QDL_CLK_PLL2_PFD2_396M]); This resulted in a register setting 0b110 for the enfc_sel mux which is reserved. Apparently this reserved setting resulted in the enfc clock being driven from pll3_pfd3_454m. This means our enfc clock was the factor 454/396 too high. With b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK") we happened to disable pll3_pfd3_454m during init, so with this commit NAND stopped working entirely on i.MX6qp. Both issues are fixed with this patch Fixes: b534f79112f0 ("clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK") Fixes: 92fd61d12723 ("clk: i.MX6: Fix enfc_sel for i.MX6dqp") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: zynqmp: rename driver specific CLK_MUX_READ_ONLYMichael Tretter2019-09-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Since commit c7cc27d006cc (clk: mux: Support CLK_MUX_READ_ONLY flag) Barebox defines the CLK_MUX_READ_ONLY flag like Linux. The ZynqMP clock driver used the flag before, because this flag is used to convey this information from the PMU firmware to the Linux driver. However, the flags of the common clock framework and the flag of the protocol between PMU firmware and the ZynqMP clock driver should be handled separately. Therefore, add a driver specific prefix to the flag definition in the ZynqMP driver. Fixes the warning drivers/clk/zynqmp/clk-mux-zynqmp.c:18:0: warning: "CLK_MUX_READ_ONLY" redefined In file included from drivers/clk/zynqmp/clk-mux-zynqmp.c:13:0: include/linux/clk.h:350:0: note: this is the location of the previous definition Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: define an enum for ldb mux inputsAhmad Fatoum2019-08-051-15/+24
| | | | | | | | | | | | | | For better readability should this code be reviewed in future, replace the hardcoded input numbers with an enum. This is just a cosmetic change and was verified to not affect clk-imx6.o. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: Fix procedure to switch the parent of LDB_DI_CLKFabio Estevam2019-08-051-3/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. The glitchy muxes are then registered as read-only. The clock parent can be selected using the assigned-clocks and assigned-clock-parents properties of the ccm device tree node: &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_MMDC_CH1_AXI>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; The issue is explained in detail in EB821 ("LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines") [1]. [1] http://www.nxp.com/files/32bit/doc/eng_bulletin/EB821.pdf Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com> Tested-by Joshua Clayton <stillcompiling@gmail.com> Tested-by: Charles Kang <Charles.Kang@advantech.com.tw> Signed-off-by: Shawn Guo <shawnguo@kernel.org> [afa: reviewed for barebox] Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> [afa: ported to barebox from Linux commit 5d283b0838] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-onlyPhilipp Zabel2019-08-052-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Kernel commit 03d576f202 ("clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only"): | Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk | tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to | enter the ldb_di_ipu_div divider. If the divider gets locked up, no | ldb_di[x]_clk is generated, and the LVDS display will hang when the | ipu_di_clk is sourced from ldb_di_clk. | | To fix the problem, both the new and current parent of the ldb_di_clk | should be disabled before the switch. As this can not be guaranteed by | the clock framework during runtime, make the ldb_di[x]_sel muxes read-only. | A workaround to set the muxes once during boot could be added to the | kernel or bootloader. | | Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> | Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> | Signed-off-by: Shawn Guo <shawnguo@kernel.org> [afa: reviewed for barebox] Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> [afa: ported from Linux kernel commit 03d576f202] [afa: added exception for i.MX6QP, see kernel commit f4a0a6c309] [afa: added cpu_has_err009219 helper function] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: remove quirky clk_set_parent(LDB_diN_sel, pll5_video_div)Ahmad Fatoum2019-08-051-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | barebox has inherited the clk_set_parent(ldb_diN_sel, pll5_video_div) from upstream kernel commit 32f3b8da22 ("ARM i.MX6q: set the LDB serial clock parent to the video PLL"), where it was enabled for all i.MX6Q revisions after 1.0. It was applied whenever CONFIG_DRIVER_VIDEO_IMX_IPUV3 was defined. The kernel removed this reparenting again as a preventive measure against ERR009219 in 03d576f202 ("clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only"). In barebox, the reparenting remains and is done for all i.MX6 SoCs with a revision > 1.0. On all of them, except for the QuadPlus and the DualPlus, this reparenting may glitch the LDB so that it permanently locks up. By removing the reparenting in this commit, producing this glitch is avoided. The device tree[1] can elect to reinstate the reparenting: &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; }; Follow-up patches will explicitly check for this and do reparenting defined this way in a glitch-free manner. As of v2019.07.0, following mainline boards are potentially broken by this (i.e. they're supported by barebox, are in the list above, had a LDB enabled and might be defining CONFIG_DRIVER_VIDEO_IMX_IPUV3): - imx6qdl-zii-rdu2.dtsi - imx6qdl-udoo.dtsi - imx6qdl-mba6x.dtsi - imx6q-var-custom.dts - imx6q-guf-santaro.dts - imx6q-embedsky-e9.dtsi [1]: If barebox is configured to show a boot splash screen, this snippet should exist in the barebox device tree. If barebox acts on it, the kernel will show following warning: ccm: ldb_di0_sel already changed from reset value: 0 ccm: ldb_di1_sel already changed from reset value: 0 This warning is safe to ignore. Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Raphael Poggi <poggi.raph@gmail.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podfPhilipp Zabel2019-08-051-0/+16
| | | | | | | | | | | | | | | | | | | | MMDC CH1 is not used on i.MX6Q, so the handshake needed to change the parent of periph2_sel or the divider of mmdc_ch1_axi_podf will never succeed. Disable the handshake mechanism to allow changing the frequency of mmdc_ch1_axi, allowing to use it as a possible source for the LDB DI clock. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> [afa: reviewed for barebox] Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> [afa: ported to barebox from Linux commit f13abeff2c] [afa: moved call site to where it would've been moved in following commit] Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx6: fix use of cpu_is_mx6* before they are initializedAhmad Fatoum2019-08-051-6/+5
| | | | | | | | | | | | | | | | | | | | | The cpu_is_mx6* macros rely on __imx_cpu_type, which is initialized dependent on device tree compatible at "postcore" init-level imx_init. The imx6q-ccm driver, which uses the cpu_is_mx6* macros, is registered at "core" init-level, however. This results on the macro always returning false. Fix this by using the cpu_mx6_is_mx6* family of macros instead. These already require that that CPU is a MX6, which is safe because the the driver only matches against "fsl,imx6q-ccm". Only exception is the video5 pll reparenting. Here we will just maintain the old behavior as we will drop the if clause in a following commit anyway. Reported-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>