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The i.MX8M ddr driver can be re-used for i.MX93, so drop the '8m' suffix
from the driver directories and Kconfig options.
Link: https://lore.barebox.org/20231110130028.2123895-2-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Currently arch specific headers can be included with #include <mach/xxx.h>.
With upcoming multi-arch support this is no longer possible as there
won't be a single mach anymore.
Move all i.MX specific header files to include/mach/imx/ to prepare for
multi-arch support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.barebox.org/20230208133519.1114700-1-l.stach@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We already have a pr_fmt, but we aren't making use of this. Change that.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20221205132835.3002605-2-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When adding a new board with a yet unsupported DDR frequency, PLL
configuration is silently skipped, leading to a later hang during DDRC
configuration. Improve the bring up user experience by printing a
warning in that case. The user is then expected to extend
imx8mm_fracpll_table, so PBL knows how PLLs should be configured for
this new frequency.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20221205132835.3002605-1-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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"GPL-2.0-or-later" was introduced in SPDX 2.0, and the old identifier
"GPL-2.0+" is now deprecated; see <https://spdx.org/licenses>.
Signed-off-by: Roland Hieber <rhi@pengutronix.de>
Link: https://lore.barebox.org/20211117113851.2022669-3-rhi@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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DRAM setup on i.MX8MP is the same as on the i.MX8MP, except for
DDRC_DDR_SS_GPR0, which the vendor's U-Boot port explicitly skips
on the nano, irrespective of the configured DRAM type. Do likewise.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20211001100949.6891-6-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This code could not decide if it was using speeds in Hz, or MHz, or just
constants that identify specific speeds.
Rework it to use symbolic constants for all speeds. Use arrays
for configurations values for all cases. The DDR DRAM speed constants
will be the array index, so the linear search for the configuration is
eliminated.
For iMX8MM type SoCs using the integr PLL the speed DDR-1067 with a 266⅔
MHz clock will now work.
The iM8MQ type SSCG PLL SoCs would previously silently program the PLL
will zero values if a non-supported DDR rate was used. Now they will
generate an error.
Note that some PLL tables have entries for speeds that the main entry
point for the code does not support, so they can't actually ever be
used. This is not fixed.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210924031446.1515172-1-tpiepho@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The i.MX8MQ uses a different PLL type than the later i.MX8M family
members, so the PLL setup did not actually work on this SoC. In U-Boot
the used PLL setup routine is a compile time decision. As we want
our DRAM init code to work for multi-image builds, this passes the
SoC type through to the PLL init, so we can use the correct setup
routine depending on the SoC we are running on.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This is a port of upstream U-Boot commit b335966958a9. Sadly there is no
more information to be found about the issue. The currently available
errata documents don't mention this issue at all and the U-Boot commit
doesn't tell much either, however this commit has been pointed out by
NXP engineers as a solution to reports of board instabilities.
| drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
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| Add logic to automatically update umctl2's setting based
| on phy training CDD value for rank to rank space issue
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| Acked-by: Ye Li <ye.li@nxp.com>
| Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
| Signed-off-by: Jacky Bai <ping.bai@nxp.com>
| Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Sascha Hauer <s.hauer@pengutronix.de> (on i.MX8MP)
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use pr_debug and pr_fmt to get a unified prefix for all messages. Also,
remove #define DEBUG at the beginning.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from
U-Boot v2020.04-rc1 with slight modifications for barebox
The i.MX8MQ boards in the tree currently use the output of an earlier
version of the NXP i.MX8M DDR Tool which doesn't use a controller driver
but instead does most stuff in board code. It seems this can coexist
with the new driver, only a few helper functions that previously lived
in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver.
Tested on an i.MX8MM EVK
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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