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* mci: imx-esdhc-pbl: Fix watermark level value for i.MXAndrey Smirnov2019-10-021-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Layerscape and i.MX have different semantics of Watermark Level Register. Whereas the former uses "0" to signify maximum allowed value, the latter does not. According to the RM (i.MX8MQ, i.MX6): "...The read burst length must be less than or equal to the read watermark level.." Setting Watermark Level Register to zero violates that limitation. It appears that, on i.MX8MQ, not following that rule causes certain configs + toolchains to result in non-bootable image. Specifically, polling for CICHB, CIDHB and DLA to clear in esdhc_send_cmd() times out. There doesn't appear to be any clear relationship as to what kind of image will have the problem, but the following combinations failed to boot on ZII i.MX8MQ Zest board: - gcc version 9.2.1 20190827 (Red Hat Cross 9.2.1-1) (GCC) + imx_v8_defconfig + CONFIG_DEBUG_LL and CONFIG_PBL_CONSOLE - gcc version 5.5.0 (Timesys 20190405) (custom toolchain) + imx_v8_defconfig Setting WML's *_BRST_LE to 16 and *_WML to 128 on i.MX resolves the issue (same setting that's selected by writing 0 on Layerscape). Fixes: 48562aeaa8 ("esdhc-xload: check for PRSSTAT_BREN only after each block") Cc: Chris Healy <cphealy@gmail.com> Cc: Ruslan Sushko <ruslan.sushko@zii.aero> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX8: Fix piggydata loadingSascha Hauer2019-08-231-8/+13
| | | | | | | | | | We are running at MX8MQ_ATF_BL33_BASE_ADDR now, so we can't use this as a temporary buffer. Add 32MiB to that address and use this instead. Also copy the piggydata to the place where we expect it later. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
* esdhc-pbl: add piggy load functionRouven Czerwinski2019-08-071-0/+46
| | | | | | | | | Add a function to load and copy the piggy data to the correct offset expected by barebox in the RAM. This way the PBL can later verify the piggydata before uncompressing and loading the main barebox. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-pbl: extract header parsing from image startRouven Czerwinski2019-08-071-14/+30
| | | | | | | | | Extract the header parsing code from esdc_start_image. The header parsing function will be used by the piggy loading code added in the next commit. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: introduce sync_caches_for_executionSascha Hauer2019-05-131-1/+3
| | | | | | | | | | | | | | | | | | | We have several places in the code which which prepares just modified code for execution. This is done differently in all the places, so add a common function to be used by all. Most places called arm_early_mmu_cache_flush(). This function includes invalidating the instruction cache, so doing it again is unnecessary. Sometimes we had arm_early_mmu_cache_flush() inside #ifdef CONFIG_MMU. The ifdef seems unnecessary since we do not have it consistently, so remove the ifdef. Some early i.MX xload code had icache_invalidate() but forgot to flush the caches. Replace the instruction cache invalidation with sync_caches_for_execution(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: invalidate icache before jumping to imageSascha Hauer2019-05-101-0/+3
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc-pbl: ls1046a: Set better divider valuesSascha Hauer2019-05-081-1/+1
| | | | | | | MMC Frequency was set to something like 55MHz. This doesn't work for all SD cards. Set to 25MHz which is supported by all SD cards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/layerscape'Sascha Hauer2019-04-081-1/+59
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| * esdhc-xload: Add support for LayerscapeSascha Hauer2019-03-131-1/+59
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mci: imx-esdhc-pbl: initialize is_beChristian Hemp2019-03-181-0/+2
|/ | | | | | | | | Initialize is_be, otherwise the value of is_be is undefined. So it is possible that the i.MX8 will not boot because the bigendian functions are used. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: check for PRSSTAT_BREN only after each blockSascha Hauer2019-03-051-9/+16
| | | | | | | | | The BREN bit tells us a watermark level sized buffer is ready for read. Instead of testing it before each FIFO read we must only check it once and then read a watermark level sized buffer. This is at least necessary on Layerscape, otherwise timeouts occur while reading the buffer. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: Add bigendian supportSascha Hauer2019-03-051-3/+10
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: Use static inline io wrappersSascha Hauer2019-03-051-27/+33
| | | | | | | We'll need big endian support for Layerscape, so put the io accessors into static inline wrappers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: move some register defines to header fileSascha Hauer2019-03-051-1/+0
| | | | | | To make them usable for the PBL driver aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: Move to drivers/mciSascha Hauer2019-03-051-0/+387
The esdhc-xload code will be used by upcoming Layerscape support aswell, so move it from architecture code to drivers/mci/. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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