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path: root/drivers/mci/imx-esdhc.h
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* mci: imx-esdhc: Layerscape: add eMMC DDR52 supportSascha Hauer2023-11-221-0/+2
| | | | | | | The Layerscape variant of the imx-esdhc also supports eMMC DDR52, add support for this mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: Layerscape: fix clock setupSascha Hauer2023-11-221-1/+1
| | | | | | | | | Set the PCS bit in the ESDHCCTL register. With this Peripheral/2 clock is used which is the clock we are actually calculating the dividers for. As the input clock is only half of the expected clock we have to account for this in set_sysctl(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: add layerscape flagSascha Hauer2023-11-221-2/+7
| | | | | | | | | | | | More Layerscape specifics are about to come. Instead of adding a specific quirk flag for each of them, rename the ESDHC_FLAG_CACHE_SNOOPING flag to ESDHC_FLAG_LAYERSCAPE to get a common layerscape flag. From looking at the Kernel driver it seems we can use these flag for the modern Layerscape SoCs, we would have to revisit this once we support LS1012. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: add uSDHC eMMC DDR52 supportAhmad Fatoum2023-04-211-0/+14
| | | | | | | | | | | | | | | | | | The uSDHC available with the i.MX6/7/8 SoCs has support for DDR clock operation. This is enabled by flipping a bit in IMX_SDHCI_MIXCTRL and adjusting the clock divider calculation to account for the automatic internal halving of the clock. Let's do that to speed up boot from eMMC. How much effect this has in practice is not constant. Comparing two Kingston eMMCs: DDR on the older v4.5 connected to an i.MX6 did not yield any difference. On the newer v5.1 one connected to an i.MX8MM, I observe a 70% improvement in sequential read throughput: from 40MiB/s to 69.5 MiB/s. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20230418093040.1865982-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Rename struct device_d to deviceSascha Hauer2023-01-101-1/+1
| | | | | | | | | | | | | The '_d' suffix was originally introduced in case we want to import Linux struct device as a separate struct into barebox. Over time it became clear that this won't happen, instead barebox struct device_d is basically the same as Linux struct device. Rename the struct name accordingly to make porting Linux code easier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.barebox.org/20221214123512.189688-3-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: sdhci: Get rid of many register opsSascha Hauer2021-06-111-1/+0
| | | | | | | | | | Most SDHCI drivers use standard readl/writel to access registers. Implement these in the common register accessor functions so that drivers only to overwrite them when they want to do something different. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210607104411.23071-12-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: sdhci: straighten capabilities registerSascha Hauer2021-06-071-7/+0
| | | | | | | | | | | So far we read the host capabilites register as two 16bit registers SDHCI_CAPABILITIES (0x40) and SDHCI_CAPABILITIES_1 (0x42). Read them as one 32bit register like Linux does. While at it switch to the register defines Linux uses. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.barebox.org/20210607104411.23071-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: Replace license and copyright boilerplate by SPDX identifiersUwe Kleine-König2020-12-071-20/+4
| | | | | | | | | Converts the files that licensecheck can determine to be licensed under GPL-2.0-only or GPL-2.0-or-later and also convert the copyright statements to SPDX. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: Share code for esdhc_send_cmd()Andrey Smirnov2019-12-041-11/+2
| | | | | | | | | | Versions of esdhc_send_cmd() in imx-esdhc.c and imx-esdhc-pbl.c implement almost the same algorithm. To avoid code repetition, move that code to imx-esdhc-common.c and adjust all of the users accordingly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: Introduce esdhc_poll()Andrey Smirnov2019-12-041-1/+3
| | | | | | | | Replace all of the explcitly coded timeout loops with a shared subroutine that is used by both regular driver and PBL code. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: Share code for esdhc_(setup|do)_data operationsAndrey Smirnov2019-12-041-0/+12
| | | | | | | | | PBL and PIO case of the regular driver do exaclty the same thing during esdhc_(setup|do)_data stages of esdhc_send_cmd(). Move the code to a common file and adjust all of the users accordingly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc-pbl: Share IO accessors with regular driverAndrey Smirnov2019-12-041-0/+98
| | | | | | | | | With a bit of a change to PBL ESDHC initialization code it is possible to share all of the low-level I/O accessor code with the regular driver, including sharing definitions of flags describing HW's quirks. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: Drop unused type definitionAndrey Smirnov2019-12-041-5/+0
| | | | | | | | There doesn't seem to be any users of struct fsl_esdhc_cfg in the tree. Drop it. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: sdhci: remove duplicate register defines for interrupt bitsSascha Hauer2019-11-211-2/+2
| | | | | | We have duplicate bit defines for the interrupt bits. Remove the duplicates. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc-pbl: Fix watermark level value for i.MXAndrey Smirnov2019-10-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Layerscape and i.MX have different semantics of Watermark Level Register. Whereas the former uses "0" to signify maximum allowed value, the latter does not. According to the RM (i.MX8MQ, i.MX6): "...The read burst length must be less than or equal to the read watermark level.." Setting Watermark Level Register to zero violates that limitation. It appears that, on i.MX8MQ, not following that rule causes certain configs + toolchains to result in non-bootable image. Specifically, polling for CICHB, CIDHB and DLA to clear in esdhc_send_cmd() times out. There doesn't appear to be any clear relationship as to what kind of image will have the problem, but the following combinations failed to boot on ZII i.MX8MQ Zest board: - gcc version 9.2.1 20190827 (Red Hat Cross 9.2.1-1) (GCC) + imx_v8_defconfig + CONFIG_DEBUG_LL and CONFIG_PBL_CONSOLE - gcc version 5.5.0 (Timesys 20190405) (custom toolchain) + imx_v8_defconfig Setting WML's *_BRST_LE to 16 and *_WML to 128 on i.MX resolves the issue (same setting that's selected by writing 0 on Layerscape). Fixes: 48562aeaa8 ("esdhc-xload: check for PRSSTAT_BREN only after each block") Cc: Chris Healy <cphealy@gmail.com> Cc: Ruslan Sushko <ruslan.sushko@zii.aero> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* esdhc-xload: move some register defines to header fileSascha Hauer2019-03-051-0/+8
| | | | | | To make them usable for the PBL driver aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: implement static inline io wrappersSascha Hauer2019-02-071-6/+0
| | | | | | | Layerscape will need accesses in big endian mode. To make this possible create static inline wrappers for the io accessors. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: esdhc: add back PIO_TIMEOUTLucas Stach2014-11-241-0/+2
| | | | | | | | | This got lost during bd1bf53b34c (mci: imx-esdhc: factor out common sdhci registers). Seems the PIO option isn't too heavily used. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: imx-esdhc: factor out common sdhci registersSascha Hauer2013-05-301-89/+0
| | | | | | | | | | | | | | | | This gives the SDHCI specific registers a common name and moves them to a separate file for use by other SDHCI like drivers. The SDHCI spec has some 16bit and 8bit registers. The i.MX accesses these as 32bit registers. These register defines now are named after the SDHCI registers they combine into one, for example: SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL is the 32bit version of the SDHCI registers HOST_CONTROL, POWER_CONTROL and BLOCK_GAP_CONTROL. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Treewide: remove address of the Free Software FoundationSascha Hauer2012-09-171-4/+0
| | | | | | | The FSF address has changed in the past. Instead of updating it each time the address changes, just drop it completely treewide. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Remove superfluous SYSCTL_RSTARoberto Nibali2012-06-301-1/+0
| | | | | Signed-off-by: Roberto Nibali <rnibali@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: Add i.MX esdhc supportSascha Hauer2010-10-111-0/+164
This adds a driver for the esdhc controller found on Freescale i.MX25/35/51 SoCs. This code is based on the U-Boot driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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