| Commit message (Collapse) | Author | Age | Files | Lines |
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Move v3 register definitions to include file so that they can
be reused for the early nand boot code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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So far we relied on the clock rate as configured by reset default or
board code. Also we did not touch the symmetric mode bit. Use
the ONFI provided timing parameters to configure the clock rate for
the Nand controller. Also symmetric mode (EDO mode) when needed.
This is done for v2 controllers (i.MX25/35) only, other controllers
need other setup code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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preset_v1_v2() still needs to distinguish between v1 and v2 and
the shared code is not very big. Since we need another v2 only
addtion in the next patch split the function into a v1 and a v2
specific function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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raw read/write was not possible because we enabled the ECC engine
during driver initialization. To support raw mode we have to disable
the ECC engine dynamically when needed. This has to be done before
the send_page function is called. The places where we have to disable
the ECC engine are not available in the driver, but are buried in the
Nand layer. To make them available we have to implement driver specific
write/read_page functions in which we configure the ECC mode.
This also makes the driver better readable as it makes the detour around
the driver internal data buffer when reading/writing pages unnecessary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The relevant informations which command is sent for which page
is already contained in the informations imx_nand_command() prints, so
remove the debug prints in send_cmd and send_addr (which only exist for
v1/v2 controllers, not for v3). Also use dev_dbg to print debug
informations instead of MTD_DEBUG.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Neither CONFIG_MXC_NAND_LOW_LEVEL_ERASE nor CONFIG_MTD_NAND_MXC_FORCE_CE
are defined anywhere, remove the code inside the ifdefs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The correct return value for a uncorrectable page is -EBADMSG, not -1
(which is -EPERM). Also the max_bitflips returned shall be the bitflips
per ecc step, not per page.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The driver returns wrong values for the ECC correction. For 2k pages
the controller reads and corrects in chunks of 512 bytes. The ECC status
register values are overwritten with each each new chunk read, so after
reading for chunks the .correct callback wil only return the ECC errors
for the last 512 byte chunk. ECC errors in the other three chunks remain
undetected.
Fix this by accumulating the ECC status while reading the chunks and
return the accumulated value in the .correct callback. Also return
-EBADMSG for a bad message and not -1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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dev_request_mem_region doesn't work properly one some SoCs on which
PTR_ERR() values clash with valid return values from dev_request_mem_region.
Replace them with dev_request_mem_resource where possible.
This patch has been generated with the following semantic patch:
// <smpl>
@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
...
- return PTR_ERR(io);
-}
+ return PTR_ERR(iores);
+}
+io = IOMEM(iores->start);
...+>
}
@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
- return PTR_ERR(io);
-}
+ return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}
@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
-if (IS_ERR(io)) {
- ret = PTR_ERR(io);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores)) {
+ ret = PTR_ERR(iores);
...
}
+io = IOMEM(iores->start);
...+>
}
@@
expression d;
expression n;
expression io;
identifier func;
@@
func(...) {
+struct resource *iores;
<+...
-io = dev_request_mem_region(d, n);
+iores = dev_request_mem_resource(d, n);
+if (IS_ERR(iores))
+ return PTR_ERR(iores);
+io = IOMEM(iores->start);
...+>
}
@@
identifier func;
@@
func(...) {
<+...
struct resource *iores;
-struct resource *iores;
...+>
}
// </smpl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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dev_request_mem_region returns an ERR_PTR, fix places which check for a
NULL pointer instead. This patch has been generated with this semantic
patch, written by me and improved by Andrey Smirnov:
// <smpl>
@@
expression e;
expression e1;
@@
e = dev_request_mem_region(...);
...
-if (!e)
- return e1;
+if (IS_ERR(e))
+ return PTR_ERR(e);
@ rule1 @
expression e;
@@
e = dev_request_mem_region(...);
@@
expression rule1.e;
identifier ret, label;
constant errno;
@@
if (!e) {
...
(
- ret = -errno;
+ ret = PTR_ERR(e);
...
goto label;
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- return -errno;
+ return PTR_ERR(e);
)
}
@depends on rule1@
expression rule1.e;
@@
- if (e == NULL)
+ if (IS_ERR(e))
{
...
}
// </smpl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
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The NFC command used for reading the result of a READID command to the NAND chip
reads 6 bytes (in x8 mode) or 6 words (in x16 mode with the upper bytes all
being 0). So there is no need to safe 16 bytes for later consumption.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There are a few NAND commands that make the chip only respond on I/O
lines 0 to 7 even for x16 devices. READID (90h) is one such command
which was already handled fine in the driver (at least for NFC v1 and
v2). Other commands (like PARAM (ECh) to read out ONFI parameters)
however were not handled properly. Instead of adding another callback
make the read_byte callback handle the holes added by the NFC and depend
on the nand-base support to call read_byte when necessary instead of
read_buf.
This fixes reading the ONFI parameter page on an i.MX25 with an x16 NAND
and probably[1] also the result of READID on i.MX51/i.MX53 with x16
NAND.
[1] untested because no matching machine available
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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tested on an i.MX25 where we now get :
nand: ONFI param page 0 valid
nand: ONFI flash detected
nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Signed-off-by: Eric Bénard <eric@eukrea.com>
Tested-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This updates the NAND stuff to Linux-3.11-rc1. It is synchronized
as best as we can get:
- locks removed
- The splitting in different files we had to better support different
features has been dropped. Instead this is now done mostly with the
use of __maybe_unused
Some barebox adjustments are forward ported, like:
- Allow partial page writes
- Optionally allow to erase bad blocks
- check for all_ff before writing a page
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This introduces the ecc stength fields in the structures and fills
them in, but leaves them unused right now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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With 2k NAND flashes the data layout in memory is not what is
written on the flash device. This leads to the result that the
factory provided bad block markers are not recognized correctly.
To preserve the factory bad block information the i.MX NAND driver
will not scan for the bad blocks itself when there is no flash based
bbt available, because the mtd layer would do so based on wrong
information. Instead, a new command is introduced which allows to
manually create a flash bbt based on the correct information.
As this command is tightly coupled to mtd and the i.MX NAND driver
the command is placed under drivers/mtd/nand/ instead of commands/
where a command normally belongs to.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To sync with the kernel.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This allows us to have some NAND specific stuff during registration,
like for example adding NAND specific device parameters.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Conflicts:
arch/arm/configs/at91sam9x5ek_defconfig
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Conflicts:
arch/arm/boards/guf-neso/lowlevel.c
arch/arm/boards/pcm038/lowlevel.c
commands/Makefile
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- remove now unused __REG definitions
- include individual SoC register files instead of imx-regs.h
- move IMX_GPIO_NR to generic.h
- finally remove imx-regs.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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On i.MX we enable all necessary clocks during startup of the clock
controller driver, so we do not need the register hacking in the drivers
anymore.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add a default case when all if(nfc_is_*) else if()
return false to prevent a compiler warning.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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platform_driver/device_register
now register_driver and register_device are for bus only usage.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- add CMD_PARAM and read_param to get the ONFI structure
- fix OOB size for flash with 224 OOB on i.MX51/3
- add the same ecc layout as the one in the kernel for
4k page flashs
Tested on an i.MX53.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Change NAND_WRITE into MTD_WRITE.
Change "page_shift" references in the core, which are purely
NAND, into mtd->writesize which is MTD generic.
Rename all "info" (struct mtd_info) into "mtd".
Also provide a parameter to add_mtd_device() so that legacy
nand devices still appear as nand<N>.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To allow for some generic io accessors introduce io.h and use
this instead of asm/io.h throughout the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The nand controller on i.MX51/53 uses two base addresses. Instead
of hardcode the second address use the new shiny resources two specify
it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The i.MX Processors support two different boot modes, the internal
boot mode and the external boot mode. Traditionally the external
NAND boot mode is handled in drivers/mtd/nand and the internal
boot mode is handled in arch/arm/mach-imx. This patch consolidates
the handling of both boot modes in arch/arm/mach-imx so that
the user does not have to look in the mtd kconfig section for
booting from NAND. Also, selecting between internal and external
boot mode now is a clear choice.
The external NAND boot mode has been independent of the mtd nand
driver, but as the code was contained in the NAND driver it was
not possible to support booting from NAND without a mtd nand driver.
This is changed with this patch.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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needed for v3 support later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This has two purposes. First we need to factor out initialization
to be able to do something different on v3 type controllers,
second with this patch we are independent of preinitialized register
values.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The v2 controller has a totally different mechanism to check
whether the data we read had ecc errors or not. Implement this.
The mechanism in the v2 controller happens to be identical to
the v3 controller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This prepares the driver for v3 support. The v3 controller
has a completely different register layout, so add a V1_V2_
namespace to the register defines to avoid confusion with
the v3 regs.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch prepares the driver to add v3 controller support
later. The v3 controller is basically the same controller as v1
and v2, but with a completely different register layout.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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NFC_SP_EN is cleared in probe and never set again, so we do not
need to clear it in other functions again.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We save/restore the value in the buffer anyway, so it makes
no difference whether we use main_area0 or main_area1. So,
we can use main_area0 and remove main_area1 from the driver
which is otherwise unused. Also, clean up the comments in
get_dev_status.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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