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* Merge branch 'for-next/mtd-nand'Sascha Hauer2020-11-101-87/+85
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| * mtd: nand: Update to Linux-5.9Sascha Hauer2020-11-101-17/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This updates the barebox NAND layer and parts of the mtd layer to Linux-5.9. This patch is huge, but the barebox NAND layer is so far away from the Linux NAND layer that a step by step update would have taken ages. Unlike Linux barebox has functions to mark a block as good. This feature has been preserved. Also barebox used to make NAND write support optional, this feature is lost during the update for the sake of better compatibility to the Linux NAND layer. This patch has been tested: - GPMI aka nand_mxs on i.MX6 - nand_imx on i.MX25 - nand_omap_gpmc on AM335x - atmel_nand on Atmel sama5d3 - nand_denali on SoCFPGA Currently untested: - nand_orion - nand_mrvl_nfc - nand_s3c24xx The nand_denali driver is tested with the update of that driver to Linux-5.9 following in the next patch. I could only test the drivers with the NAND chips found on my boards, so there's still enough room for regressions, especially given that the NAND drivers themselves are mostly not updated. With the NAND layer being up-to-date with Linux it should hopefully be easy to update drivers to their Linux counterpart as well if necessary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand: gpmi: Use nand_to_mtd()Sascha Hauer2020-11-091-1/+1
| | | | | | | | | | | | | | We have a function for getting from the struct nand_chip * to the struct mtd_info *, so use it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand: move function hooks to struct nand_legacySascha Hauer2020-11-091-20/+20
| | | | | | | | | | | | | | Linux had moved the traditional nand function hooks to an extra struct nand_legacy. Do the same in barebox for compatibility. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: rename class_dev to devSascha Hauer2020-11-091-2/+2
| | | | | | | | | | | | | | | | The mtds own device is named 'dev' in the Kernel whereas it's named 'class_dev' in barebox. Rename it to 'dev' for better compatilibility to the Kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: Use classdev->parentSascha Hauer2020-11-091-2/+2
| | | | | | | | | | | | | | | | | | | | Instead of mtd->parent we can use mtd->classdev.parent which points to the same device. With this we can remove the 'parent' member of struct mtd_info. This member exists in the Linux kernel as well, but is of type struct mtd_info, so this is done as preparation to re-add mtd->parent with the same type as in Linux. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: Add underscore prefix to mtd hooksSascha Hauer2020-11-061-9/+9
| | | | | | | | | | | | | | In the Kernel the mtd function hooks begin with an underscore. Do the same in barebox to be better comparable to the Kernel. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand: Pass struct nand_chip aroundSascha Hauer2020-11-061-56/+51
| | | | | | | | | | | | | | | | | | Traditionally Linux passed a struct mtd_info * around as context between the different functions. This has been changed to a struct nand_chip *. Do the same for barebox as well as another step towards updating the NAND layer to current Linux. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mtd: nand-mxs: fix out-of-bounds write on 64-bit SoCsAhmad Fatoum2020-10-091-3/+1
|/ | | | | | | | | | | Probing the nand_mxs device driver on 64 bit systems invokes undefined behavior, because of an errant cast. Fix this. No change of behavior for 32-bit SoCs intended. On error, type == 0 == GPMI_MXS as it used to. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: Embed struct mtd_info into struct nand_chipSascha Hauer2019-08-261-4/+2
| | | | | | | | | Similar to what is done in the Kernel. In the Kernel we have a struct nand_device embedded into struct nand_chip and the nand_device has an mtd_info embedded into it. Until we have struct nand_device we embed mtd_info directly into the nand_chip. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: Add and use static inline wrapper for getting nand_chip from mtdSascha Hauer2019-08-261-14/+14
| | | | | | | | | All drivers in tree use mtd->priv for the nand_chip. Add and use a static inline wrapper mtd_to_nand() which we already have in the kernel for getting the nand_chip from the mtd_info struct. Next step would be to embed a struct mtd_info into struct nand_chip. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: Make ecc strength configurable via device treeSascha Hauer2019-08-061-4/+21
| | | | | | | | | | | According to the binding doc the mxs NAND driver supports the "nand-ecc-strength" and "nand-ecc-step-size" options. This adds support for these options to the driver. The "nand-ecc-step-size" is not really configurable, the only accepted value is 512 so this is merely to sanity check that there's nothing specified that we can't yet support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: inline only once used functionSascha Hauer2019-08-061-6/+1
| | | | | | | mxs_nand_ecc_size_in_bits() is used only once and is simple enough to be inlined. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: pass mtd_info to mxs_nand_get_mark_offset()Sascha Hauer2019-08-061-6/+5
| | | | | | | struct mtd_info * contains everything mxs_nand_get_mark_offset() needs, so pass this pointer rather than several integer arguments. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: change API between NAND driver and fcb codeSascha Hauer2019-08-061-29/+33
| | | | | | | | | | | | The imx-bbu-nand-fcb update handler code calls into the NAND driver to get the ecc strength and bad block marker position. Change the API so that only a single function is necessary and not three functions. Also in future the ecc strength will be configurable via device tree. This means static parameters like page size / oob size are no longer enough to calculate the ecc strength and so we store a pointer to our mtd_info struct in a static global variable. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: Make locally used variable staticSascha Hauer2019-08-061-3/+1
| | | | | | | fake_ecc_layout is only used in the mxs nand driver, so make it static. Also it's not necessary to zero the structure. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: calculate ecc_strength only onceSascha Hauer2019-08-061-12/+36
| | | | | | | | | | Instead of calculating the ecc strength multiple times with each page read just do it once and store the result in chip->ecc.strength. While at it also store the correct value in chip->ecc.bytes instead of writing a bogus value into it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: consistently rename struct nand_chip * to "chip"Sascha Hauer2019-08-061-74/+74
| | | | | | | The struct nand_chip * is sometimes named "nand" and sometimes "chip". For consistency name it "chip" throughout the driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand: nand_mxs: Do not zero out DMA coherent memoryAndrey Smirnov2019-05-281-3/+0
| | | | | | | | Memory returned by dma_alloc_coherent() should already be zeroed out, so there's no need to do this explicitly. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Revert "mtd: nand: Kill the chip->scan_bbt() hook"Sascha Hauer2019-01-211-9/+18
| | | | This reverts commit 95ce69795506293eae28d6e64055d2c7ae27f164.
* mtd: nand: Kill the chip->scan_bbt() hookLadislav Michl2018-12-171-18/+9
| | | | | | | | | | | Linux commit e80eba758151 adapted for Barebox: None of the existing drivers are overloading the ->scan_bbt() method, let's get rid of it and replace calls to ->scan_bbt() by nand_create_bbt() ones. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: mxs: make locally used functions staticSascha Hauer2018-10-181-2/+2
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: gpmi-nand: Make sure clock is disabled during rate changeSascha Hauer2018-07-061-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On i.MX6 GPMI Nand controller the clock must be disabled during a rate change. Otherwise glitches on the clock line may occur which result in errors like: MXS NAND: Error sending command MXS NAND: DMA read error There were previous attempts to fix this. One is in: 54961378f0 imx6: clk: Gate off ENFC clock before setting clock rate This patch added a clk_disable() right before the rate change. Since a clk_disable() on a disabled clk is a no-op, the patch added a clk_enable() to the i.MX6 clk driver in the hope that the clk is enabled in the nand driver probe and the clk_disable() really takes place. This patch doesn't work. First of all it enabled the enfc_podf clk which was not the one that was actually disabled in the nand driver, resulting in the nand drivers call to clk_disable() still being a no-op. Then this patch also only works only on the classic i.MX6 which was the only one supported at that time, but not on the i.MX6UL, i.MX6SX and i.MX6SL which have a separate clk driver. Instead of adding more quirks to the other i.MX6 clk drivers, fix this in the GPMI driver. We no longer call clk_disable() on a disabled clk, but instead do a clk_enable() first which makes sure the hardware state is synchronized to the usage count and the following clk_disable() is really effective. At the same time we can (and actually must) remove the quirk in the i.MX6 clk driver. Also add clk_disable()/clk_enable() around another rate change in the GPMI driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: nand_mxs: Don't call get/set features on chips which do not ↵Sascha Hauer2017-09-061-9/+13
| | | | | | | | | support it Older versions of the ONFI spec do not support get/set features, so do not call these commands when they are not available. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: improve error messagesUwe Kleine-König2017-09-061-2/+2
| | | | | | | | This commit adds the return value of the failing function to one message and makes the other unique. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: nand_mxs: Fix readtotal calculationChristian Hemp2016-11-111-4/+4
| | | | | | | | | | | | | | | | | | | | | The calculation of readtotal must be bit alligend. If not the bch core finds bit flips in every page, because readtotal is too small. This bug was mostly introduced since commit "51061a9 mtd: nand: nand_mxs: Add subpage read support". Tested with: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion S34ML08G2), 1024MiB, page size: 2048, OOB size: 128 nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron MT29F4G08ABADAWP), 512MiB, page size: 2048, OOB size: 64 nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND 1GiB 3,3V 8-bit), 1024MiB, page size: 2048, OOB size: 64 Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand: imx6: Changed default NAND clockDaniel Schultz2016-11-111-1/+1
| | | | | | | | | | | | | | | The Barebox recognized false bad erase blocks while booting from a Spansion NAND (1). This error occurred due a to high clock. The Kernel sets the default NAND clock to 22Mhz. So, to fix this error and to be more identical with the Kernel, the Barebox should be too. 1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion S34ML08G2), 1024MiB, page size: 2048, OOB size: 128 Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de> Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand_mxs: Setup timingSascha Hauer2016-06-241-4/+808
| | | | | | | | So far we relied on the default timing values which are rather slow. This patch adds the timing setup functions from the kernel. Tested on i.MX6 with a AMD/Spansion S34ML08G2 and a Micron MT29F32G08ABAAAWP. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: gpmi: Use subpage reads only on suitable NAND chipsSascha Hauer2016-06-221-3/+5
| | | | | | | | | On some NAND chips the driver uses a ECC size that is not dividable by the number of chunks per page which means a single chunk cannot be read. Disable the subpage feature for these NANDs. This is quite unfortunate since the subpage feature really speeds up scanning NAND chips. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: nand_mxs: Add subpage read supportSascha Hauer2016-05-101-8/+47
| | | | | | | | | subpage read support can significantly speed up scanning UBI volumes, so add support for it. This is inspired by the corresponding Kernel commit. Unlike in the kernel we add subpage read support for i.MX28 aswell. Testing it on i.MX28 revealed no problems. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: nand_mxs: Factor out BCH setup functionSascha Hauer2016-05-101-31/+28
| | | | | | | The BCH setup has to be changed during runtime with the following patches, so factor out a function for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* driver: replace dev_request_mem_region with dev_request_mem_resourceSascha Hauer2016-03-071-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region doesn't work properly one some SoCs on which PTR_ERR() values clash with valid return values from dev_request_mem_region. Replace them with dev_request_mem_resource where possible. This patch has been generated with the following semantic patch: // <smpl> @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { ... - return PTR_ERR(io); -} + return PTR_ERR(iores); +} +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) - return PTR_ERR(io); -} + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { - ret = PTR_ERR(io); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { + ret = PTR_ERR(iores); ... } +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ identifier func; @@ func(...) { <+... struct resource *iores; -struct resource *iores; ...+> } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: gpmi: Add erased page bitflip correctionMarkus Pargmann2016-01-041-2/+40
| | | | | | | | | | | | | | Hardware ECC does not work for erased pages. However as soon as something that is not 0xff is found in the page, hardware ECC assumes this is valid data and produces an uncorrectable error ECC status. We can use that to check for bitflips in erased pages and fix them if the number of flipped bits is below the ecc_strength. We need to move the memcpy above the for loop to be able to access the buffer directly. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: use 'const void *' for struct of_device_id.dataAntony Pavlov2015-04-301-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 2011 barebox' of_device_id struct uses unsigned long type for data field: struct of_device_id { char *compatible; unsigned long data; }; Almost always struct of_device_id.data field are used as pointer and need 'unsigned long' casting. E.g. see 'git grep -A 4 of_device_id drivers/' output: drivers/ata/sata-imx.c:static __maybe_unused struct of_device_id imx_sata_dt_ids[] = { drivers/ata/sata-imx.c- { drivers/ata/sata-imx.c- .compatible = "fsl,imx6q-ahci", drivers/ata/sata-imx.c- .data = (unsigned long)&data_imx6, drivers/ata/sata-imx.c- }, { Here is of_device_id struct in linux kernel v4.0: struct of_device_id { char name[32]; char type[32]; char compatible[128]; const void *data; }; Changing of_device_id.data type to 'const void *data' will increase barebox' linux kernel compatibility and decrease number of 'unsigned long' casts. Part of the patch was done using the 'coccinelle' tool with the following semantic patch: @rule1@ identifier dev; identifier type; identifier func; @@ func(...) { <... - dev_get_drvdata(dev, (unsigned long *)&type) + dev_get_drvdata(dev, (const void **)&type) ...> } @rule2@ identifier dev; identifier type; identifier func; identifier data; @@ func(...) { <... - dev_get_drvdata(dev, (unsigned long *)&type->data) + dev_get_drvdata(dev, (const void **)&type->data) ...> } Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: move DMA alloc functions to dma.hLucas Stach2015-03-061-1/+1
| | | | | | | | | | This better separates the DMA from the MMU functionality. Also move all drivers that only depends on asm/mmu.h for the alloc functions over to the common header. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: change dma_alloc/free_coherent to match other architecturesLucas Stach2015-03-061-2/+3
| | | | | | | | | As a lot drivers currently rely on the 1:1 virt->phys mapping on ARM we define DMA_ADDRESS_BROKEN to mark them. In order to use them on other architectures with a different mapping they need proper fixing. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX6: use generic calculation in nand bbu handlerStefan Christ2015-01-291-3/+4
| | | | | | | | | | | The parameters ECC Strength, BadBlockMarkerByte and BadBlockMarkerStartBit in the FCB structure depends on the nand chip's pagesize and oobsize. Instead of hardcoding these values into the imx6 bbu handler calculate these values on the fly. Therefore we export the necessary functions from the nand_mxs driver to use them in the bbu handler. Signed-off-by: Stefan Christ <s.christ@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* imx6: clk: Gate off ENFC clock before setting clock rateDmitry Lavnikevich2014-11-261-0/+1
| | | | | | | | | This fixes NAND initialization issue which appears occasionally on some i.MX6 SoCs (particulary was observed on phyCARD-i.MX6 with i.MX6Solo). Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* resource: Let dev_request_mem_region return an error pointerSascha Hauer2014-09-161-0/+5
| | | | | | For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: mxs: Fix 2k nand with oob size of 224 bytesSascha Hauer2014-05-201-16/+0
| | | | | | | | | | | | | The mxs nand driver has a calculation for the ecc strength. This calculation was not used for some common nands and it was assumed that 2k page nands always have a ecc strength of 8. This is not true since there are devices with 224 bytes of oob instread of 64 bytes. These allow for a greater ecc strength. Since the kernel relies on the calculation and we have to be consistent with the kernel use the calculcation in barebox aswell and just remove our assumptions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-mxs: Return bitflipsSascha Hauer2014-04-291-1/+4
| | | | | | | The read_page hook shall return the number of bitflips. Implement that. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand: mxs: Fix for calculating ecc strength on some types of NAND flashDmitry Lavnikevich2014-03-121-4/+17
| | | | | | | | | | | | | Was tested on NAND with {writesize=4096, oobsize=224} and {writesize=2048, oobsize=64}. This patch will not break any NAND that was working before. Implemented calculation way may be used for other NAND chips with writesize == 2048 but oobsize != 64. Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Grigory Milev <g.milev@sam-solutions.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand: mxs: Check for up to 4 NAND chipsDmitry Lavnikevich2014-03-121-2/+9
| | | | | | | | | | Since i.MX6 has only one R/B actual pin, if there are several R/B signals (from different NAND chips) they must be connected to this pin. Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Grigory Milev <g.milev@sam-solutions.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand_mxs: fix on i.MX28Eric Bénard2013-09-101-0/+1
| | | | | | | | | | when the bootmode is different than NAND (USB for example), the GPMI clock is not enabled thus we can't probe a NAND flash. Tested on an i.MX28 Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: mxs-nand: Add on flash bbt supportSascha Hauer2013-07-231-0/+13
| | | | | | For DT only at the moment. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: mxs-nand: Add i.MX6 supportSascha Hauer2013-07-231-22/+80
| | | | | | | The i.MX6 uses the same GPMI NAND controller as i.MX23/28 do. This adds i.MX6 support to the driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: gpmi: cleanup includesSascha Hauer2013-07-231-3/+1
| | | | | | remove unused includes and use <io.h> instead of <asm/io.h> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: gpmi: replace MXS_BCH_BASE with driver resourcesSascha Hauer2013-07-231-6/+8
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: gpmi: use io_base instead of MXS_GPMI_BASESascha Hauer2013-07-231-3/+2
| | | | | | | we have io_base, so use it instead of hardcoded base address. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dma: apbh: Turn into a driverSascha Hauer2013-07-231-3/+0
| | | | | | This converts the apbh driver into a real driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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