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* ARM: start: Fix image size calculationSascha Hauer2017-02-081-1/+1
| | | | | | | | | | In barebox_non_pbl_start() we do not run at the address we are linked at, so we must read linker variables using ld_var(). Since ld_var() current is not available on arm64 we create two zero sized arrays, one at the begin of the image and one at the end. The difference between both is the image size we are looking for. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: nand_mxs: Fix readtotal calculationChristian Hemp2016-11-111-4/+4
| | | | | | | | | | | | | | | | | | | | | The calculation of readtotal must be bit alligend. If not the bch core finds bit flips in every page, because readtotal is too small. This bug was mostly introduced since commit "51061a9 mtd: nand: nand_mxs: Add subpage read support". Tested with: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion S34ML08G2), 1024MiB, page size: 2048, OOB size: 128 nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xdc (Micron MT29F4G08ABADAWP), 512MiB, page size: 2048, OOB size: 64 nand: NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND 1GiB 3,3V 8-bit), 1024MiB, page size: 2048, OOB size: 64 Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Lengfeld <s.lengfeld@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand: imx6: Changed default NAND clockDaniel Schultz2016-11-111-1/+1
| | | | | | | | | | | | | | | The Barebox recognized false bad erase blocks while booting from a Spansion NAND (1). This error occurred due a to high clock. The Kernel sets the default NAND clock to 22Mhz. So, to fix this error and to be more identical with the Kernel, the Barebox should be too. 1: nand: NAND device: Manufacturer ID: 0x01, Chip ID: 0xd3 (AMD/Spansion S34ML08G2), 1024MiB, page size: 2048, OOB size: 128 Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Tested-by: Stefan Lengfeld <s.lengfeld@phytec.de> Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd'Sascha Hauer2016-10-101-30/+26
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| * nand: denali: get rid of compile-time debug informationSteffen Trumtrar2016-09-261-12/+0
| | | | | | | | | | | | | | | | Remove dev_dbgs containing __FILE__ and __LINE__ and no other interesting debug informations. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * nand: denali: use is_timeout in while loopSteffen Trumtrar2016-09-261-16/+23
| | | | | | | | | | | | | | | | | | Instead of using udelay and a countdown, use the is_timeout function. Also, move the code closer to the kernel version, i.e. check for the correct bank and clean the interrupt status. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * nand: denali: use correct interrupts in read_pageSteffen Trumtrar2016-09-261-2/+3
| | | | | | | | | | | | | | | | The interrupt mask is incorrect in case of HW error correction. The driver will time out waiting for the wrong interrupts. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mtd: imx-nand: Move v3 register definitions to include fileSascha Hauer2016-09-221-49/+0
|/ | | | | | | Move v3 register definitions to include file so that they can be reused for the early nand boot code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-imx: Optimize timing for i.MX25Sascha Hauer2016-08-181-0/+30
| | | | | | | | | | | So far we relied on the clock rate as configured by reset default or board code. Also we did not touch the symmetric mode bit. Use the ONFI provided timing parameters to configure the clock rate for the Nand controller. Also symmetric mode (EDO mode) when needed. This is done for v2 controllers (i.MX25/35) only, other controllers need other setup code. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand-imx: split preset_v1_v2 into two functionsSascha Hauer2016-08-181-13/+29
| | | | | | | | | preset_v1_v2() still needs to distinguish between v1 and v2 and the shared code is not very big. Since we need another v2 only addtion in the next patch split the function into a v1 and a v2 specific function. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: add ONFI timing mode to nand_timings converterSascha Hauer2016-08-182-1/+252
| | | | | | | | | | | Ported from Linux commit 974647e: | Add a converter to retrieve NAND timings from an ONFI NAND timing mode. | At the moment, only SDR NAND timings are supported. | | Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* nand: mrvl: use ERR_CAST() for returning error pointersSascha Hauer2016-07-251-3/+3
| | | | | | | | | | | ERR_CAST exists to return error pointers as error pointers without casting them explicitly to the correct pointer type. Also this Fixes: In function 'alloc_nand_resource': warning: return makes pointer from integer without a cast Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd'Sascha Hauer2016-07-112-10/+815
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| * mtd: nand_mxs: Setup timingSascha Hauer2016-06-241-4/+808
| | | | | | | | | | | | | | | | So far we relied on the default timing values which are rather slow. This patch adds the timing setup functions from the kernel. Tested on i.MX6 with a AMD/Spansion S34ML08G2 and a Micron MT29F32G08ABAAAWP. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand: Set ONFI function hooks earlierSascha Hauer2016-06-241-6/+7
| | | | | | | | | | | | | | | | Make the ONFI function hooks available after nand_scan_ident() but before nand_scan_tail(). Based on the kernel commit: 4204ccc mtd: set ONFI nand's default hooks in nand_set_defaults() Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2016-07-111-4/+1
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| * | mtd: nand: simplify nand_block_checkbadUwe Kleine-König2016-07-051-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if (A) { if (!B) return C; return D; } return C; can be simplified to: if (A && B) return D; return C; Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2016-07-111-17/+16
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| * | mtd: nand: imx-bbm: use raw reading when checking for factory BBMUwe Kleine-König2016-07-111-17/+16
| |/ | | | | | | | | | | | | | | | | | | This is necessary to prevent the imx_nand_bbm command to bail out on ECC errors which leaves the device without BBT. Also simplify buffer management: Use on-stack buffer instead of malloc. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / mtd: nand: gpmi: Use subpage reads only on suitable NAND chipsSascha Hauer2016-06-221-3/+5
|/ | | | | | | | | On some NAND chips the driver uses a ECC size that is not dividable by the number of chunks per page which means a single chunk cannot be read. Disable the subpage feature for these NANDs. This is quite unfortunate since the subpage feature really speeds up scanning NAND chips. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: nand_mxs: Add subpage read supportSascha Hauer2016-05-101-8/+47
| | | | | | | | | subpage read support can significantly speed up scanning UBI volumes, so add support for it. This is inspired by the corresponding Kernel commit. Unlike in the kernel we add subpage read support for i.MX28 aswell. Testing it on i.MX28 revealed no problems. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: Pass page argument to read_subpage hookSascha Hauer2016-05-101-2/+2
| | | | | | | Similar to what the kernel does in e004debda (mtd: nand: add "page" argument for read_subpage hook). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: nand_mxs: Factor out BCH setup functionSascha Hauer2016-05-101-31/+28
| | | | | | | The BCH setup has to be changed during runtime with the following patches, so factor out a function for it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd'Sascha Hauer2016-05-091-54/+42
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| * mtd: nand: omap_gpmc: Fix bitflips in empty pageTeresa Remmet2016-04-121-20/+42
| | | | | | | | | | | | | | | | | | | | | | When using BCH8 decoding, bitflips in an empty page are not checked. This can cause issues if UBI/UBIFS are used. Extend the omap_correct_bch() function to check for them. Code is based on linux mainline mtd/nand/omap2.c driver. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand: omap_gpmc: Remove BCH4 supportTeresa Remmet2016-04-121-35/+1
| | | | | | | | | | | | | | This has no users and seems to be untested. Removed it. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | stdio: rename getc to getcharSascha Hauer2016-04-151-1/+1
| | | | | | | | | | | | | | The function we have implemented as getc has the semantics of the standard function getchar, so rename it accorgingly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | string: Fix (v)asprintf prototypesSascha Hauer2016-04-151-1/+1
|/ | | | | | | | | | Our asprintf and vasprintf have different prototypes than the glibc functions. This causes trouble when we want to share barebox code with userspace code. Change the prototypes for (v)asprintf to match the glibc prototypes. Since the current (v)asprintf are convenient to use change the existing functions to b(v)asprintf. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd-imx-nand'Sascha Hauer2016-04-081-102/+139
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| * mtd: nand-imx: fix raw read/writeSascha Hauer2016-03-171-28/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | raw read/write was not possible because we enabled the ECC engine during driver initialization. To support raw mode we have to disable the ECC engine dynamically when needed. This has to be done before the send_page function is called. The places where we have to disable the ECC engine are not available in the driver, but are buried in the Nand layer. To make them available we have to implement driver specific write/read_page functions in which we configure the ECC mode. This also makes the driver better readable as it makes the detour around the driver internal data buffer when reading/writing pages unnecessary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand-imx: remove/replace debug printSascha Hauer2016-03-171-5/+1
| | | | | | | | | | | | | | | | | | | | The relevant informations which command is sent for which page is already contained in the informations imx_nand_command() prints, so remove the debug prints in send_cmd and send_addr (which only exist for v1/v2 controllers, not for v3). Also use dev_dbg to print debug informations instead of MTD_DEBUG. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand-imx: remove dead codeSascha Hauer2016-03-171-45/+0
| | | | | | | | | | | | | | Neither CONFIG_MXC_NAND_LOW_LEVEL_ERASE nor CONFIG_MTD_NAND_MXC_FORCE_CE are defined anywhere, remove the code inside the ifdefs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand-imx: Fix correct_data return value for v2/v3 controllersSascha Hauer2016-03-171-12/+6
| | | | | | | | | | | | | | | | The correct return value for a uncorrectable page is -EBADMSG, not -1 (which is -EPERM). Also the max_bitflips returned shall be the bitflips per ecc step, not per page. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand-imx: Fix v1 controller ECC codeSascha Hauer2016-03-171-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver returns wrong values for the ECC correction. For 2k pages the controller reads and corrects in chunks of 512 bytes. The ECC status register values are overwritten with each each new chunk read, so after reading for chunks the .correct callback wil only return the ECC errors for the last 512 byte chunk. ECC errors in the other three chunks remain undetected. Fix this by accumulating the ECC status while reading the chunks and return the accumulated value in the .correct callback. Also return -EBADMSG for a bad message and not -1. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mtd: nand: export nand_check_erased_bufSascha Hauer2016-04-081-1/+1
| | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mtd: rename mtd_all_ff -> mtd_buf_all_ffSascha Hauer2016-03-151-1/+1
| | | | | | | | | | | | | | To make clear this function checks a given buffer and not data on a mtd device. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | mtd: Add support for marking blocks as goodSascha Hauer2016-03-151-0/+59
|/ | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mtd'Sascha Hauer2016-03-112-3/+3
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| * mtd: nand: default bitflip-reporting threshold to 75% of correction strengthSascha Hauer2016-03-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on Kernel commit 240181fd0ffa6 from Brian Norris: The MTD API reports -EUCLEAN only if the maximum number of bitflips found in any ECC block exceeds a certain threshold. This is done to avoid excessive -EUCLEAN reports to MTD users, which may induce additional scrubbing of data, even when the ECC algorithm in use is perfectly capable of handling the bitflips. This threshold can be controlled by user-space (via sysfs), to allow users to determine what they are willing to tolerate in their application. But it still helps to have sane defaults. In recent discussion [1], it was pointed out that our default threshold is equal to the correction strength. That means that we won't actually report any -EUCLEAN (i.e., "bitflips were corrected") errors until there are almost too many to handle. It was determined that 3/4 of the correction strength is probably a better default. [1] http://lists.infradead.org/pipermail/linux-mtd/2015-January/057259.html Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: Fix erasing of devices >4GiBSascha Hauer2016-02-091-1/+1
| | | | | | | | | | | | | | | | | | When a device >4GiB is erased, not only the offset can be bigger than 4GiB, but also the size. This happens with the simplest command to erase a device: erase /dev/nand0. Make the size argument a 64bit type to make this work. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mtd: nand-bb: Fix 8k page size nandsSascha Hauer2016-02-091-1/+1
| | | | | | | | | | | | | | As the comment states BB_WRITEBUF_SIZE must be a multiple of the largest NAND page size. Since this is 8192 and not 4096, change it accordingly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | driver: replace dev_request_mem_region with dev_request_mem_resourceSascha Hauer2016-03-078-32/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region doesn't work properly one some SoCs on which PTR_ERR() values clash with valid return values from dev_request_mem_region. Replace them with dev_request_mem_resource where possible. This patch has been generated with the following semantic patch: // <smpl> @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { ... - return PTR_ERR(io); -} + return PTR_ERR(iores); +} +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) - return PTR_ERR(io); -} + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); -if (IS_ERR(io)) { - ret = PTR_ERR(io); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) { + ret = PTR_ERR(iores); ... } +io = IOMEM(iores->start); ...+> } @@ expression d; expression n; expression io; identifier func; @@ func(...) { +struct resource *iores; <+... -io = dev_request_mem_region(d, n); +iores = dev_request_mem_resource(d, n); +if (IS_ERR(iores)) + return PTR_ERR(iores); +io = IOMEM(iores->start); ...+> } @@ identifier func; @@ func(...) { <+... struct resource *iores; -struct resource *iores; ...+> } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | driver: Fix return check of dev_request_mem_regionSascha Hauer2016-02-232-7/+7
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dev_request_mem_region returns an ERR_PTR, fix places which check for a NULL pointer instead. This patch has been generated with this semantic patch, written by me and improved by Andrey Smirnov: // <smpl> @@ expression e; expression e1; @@ e = dev_request_mem_region(...); ... -if (!e) - return e1; +if (IS_ERR(e)) + return PTR_ERR(e); @ rule1 @ expression e; @@ e = dev_request_mem_region(...); @@ expression rule1.e; identifier ret, label; constant errno; @@ if (!e) { ... ( - ret = -errno; + ret = PTR_ERR(e); ... goto label; | - return -errno; + return PTR_ERR(e); ) } @depends on rule1@ expression rule1.e; @@ - if (e == NULL) + if (IS_ERR(e)) { ... } // </smpl> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
* Introduce include/linux/spinlock.hYegor Yefremov2016-02-011-0/+1
| | | | | | | Move spinlock related definitions to its original place. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: gpmi: Add erased page bitflip correctionMarkus Pargmann2016-01-041-2/+40
| | | | | | | | | | | | | | Hardware ECC does not work for erased pages. However as soon as something that is not 0xff is found in the page, hardware ECC assumes this is valid data and produces an uncorrectable error ECC status. We can use that to check for bitflips in erased pages and fix them if the number of flipped bits is below the ecc_strength. We need to move the memcpy above the for loop to be able to access the buffer directly. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: Add erased page bitflip check helper functionsMarkus Pargmann2016-01-041-0/+128
| | | | | | | | | | This adds the bitflip check helper functions from the kernel. They are used to check for bitflips in erased pages and correct them in the buffer so that UBI can work with it. Unfortunately most nand controllers do not have ECC for erased pages and don't do this on their own. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08USebastian Hesselbarth2015-11-231-0/+1
| | | | | | | | This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XPSebastian Hesselbarth2015-11-232-3/+12
| | | | | | | | | | | Marvell PXA3xx and Armada 370/XP share the same NAND controller IP with some minor differences. With support for controller IP v2, now allow to build the driver on Armada 370/XP. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand_mrvl_nfc: Add support for NDCB3 registerSebastian Hesselbarth2015-11-231-1/+10
| | | | | | | | | | Newer versions of PXA3xx NAND controller support a 4th Command Buffer register. Add the required HWFLAGS and additional write to NDCB0. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand_mrvl_nfc: Add support for HW BCH ECCSebastian Hesselbarth2015-11-231-1/+25
| | | | | | | | Add support for HW BCH ECC for those HW versions that support it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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