| Commit message (Collapse) | Author | Age | Files | Lines |
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Add compatible for the GEM on the Zynq 7000 device.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Both pclk and hclk are required clocks in the DT binding.
rx_clk and tx_clk are optional, but must be enabled if a system
has separate gates for them.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The U-Boot dwc_eth_qos driver ported in the previous commit had support
for both the Tegra 186/194 and STM32MP variants of the EQOS IP.
The barebox Tegra supported doesn't include the 186, but as the driver
was nevertheless ported along with the rest, lets include it in the
source tree.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We already have Designware NIC support in barebox, but for the DWMAC1000,
the DWMAC4 (also called GMAC4), no support was mainline so far.
The DWMAC4 is different enough that sharing code with the DWMAC1000 is
not really that helpful, because even basics like MDIO registers have
different layout. Instead of coding bit masks and shifts into the driver
data, like Linux does, we'll keep both driver kinds separate.
Nevertheless, we collect functions that are not SoC-specific into a
separate 'library' file.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Barebox-version of the Linux v5.2 patch:
40ae25505fe834648ce4aa70b073ee934942bfdb
net: stmmac: socfpga: fix phy and ptp_ref setup for Arria10/Stratix10
On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from
the Cyclone5 and Arria5:
- The emac PHY setup bits are in separate registers.
- The PTP reference clock select mask is different.
- The register to enable the emac signal from FPGA is different.
Thus, this patch creates a separate function for setting the phy modes on
Arria10/Agilex/Stratix10. The separation is based a new DTS binding:
"altr,socfpga-stmmac-a10-s10".
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
The new DTS binding is already part of v2019.10.0 and the driver doesn't
probe on Arria10 without the new binding introduced in this patch.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Ethernet support for ar9331 is upstream now. So, drop every thing what
is provided by upstream devicetree and rename compatible in the driver.
barebox network driver will need more work to be upstream compliant. For
example we should not request or touch the gmac register directly. Since
currently it is not clear how this should be implemented, patch the
upstream dts with reg-names = "ge0", "gmac".
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Based on a unpublished patch from Andrew Lunn:
When the switch is hardware reset, it reads the contents of the
EEPROM. This can contain instructions for programming values into
registers and to perform waits between such programming. Reading
the EEPROM can take longer than the 100ms
mv88e6xxx_hardware_reset() waits after deasserting the reset
GPIO. So poll the EEPROM done bit to ensure it is complete.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
orignal patch augmented to have necessary Global 1 plubming, ported to
Barebox and slightly changed.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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s/MIDO/MDIO
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When the driver is not able to get or control the phy regulator memory
resources are already acquired and need to be released during rollback.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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NETX support has been removed from barebox, so remove the ethernet
driver as well.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This makes of_phy_device_connect() work properly when the phy is
specified in the device tree. Without it of_mdio_find_phy() will
not find the right device. It will match:
bus->parent->device_node == phy_node->parent
Without this patch bus->parent->device_node will be the ethernet node
and phy_node->parent will be the ti,cpsw-mdio node. With the MDIO device
node registered as device of its own both nodes above will be the
ti,cpsw-mdio node.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Tested on Microchip SAMA5D27 SOM1 EK1
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Microchip SAMA5D27 has more then one TX queue. So it will
go in to TX timeout if only one was initialized.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The ! operator is applied wrongly to only smc91xx_reg_read's return value,
when probably the intention was for it to apply to the whole expression.
However, wait_on_timeout keeps looping while the condition is false,
so dropping the ! is the right thing to do. Do the right thing.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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There's already an .ops member two lines later. Remove one.
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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at least imx28-evk need it to work with devicetree
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Upstream device trees no longer have a "cpsw-phy-sel" property to find
the phy_sel register, instead they have a child device of the pinctrl
node compatible to "ti,am3352-phy-gmii-sel". Also the "rmii-clock-ext"
property is no longer global to the cpsw but instead can be selected
per slave. To adopt to these changes take the short way out for now
and find the new node by its compatible and hardcode the "rmii-clock-ext"
setting (which is set to true in am33xx-l4.dtsi and not overwritten
by any board).
This makes the cpsw driver work again. Tested on Beaglebone black
board.
Fixes: 1dc748b3b2 ("dts: update to v5.1-rc1")
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Receive buffers are properly synchronized only if Cadence is
GEM. Fix it for MACB as well.
Fixes: 86dc5259e25d (net: macb: no need for coherent memory for receive buffer)
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In Linux, '---help---' was deprecated in favor of 'help', and
this is checked by the recent checkpatch.pl
See Linux commit 84af7a6194e493fae312a2b7fa5a3b51f76d9282
The number of '---help---' is gradually decreasing in Linux, but there
are still lots. However, '---help---' will be completely killed when
the time comes.
Fortunately, there are only some in Barebox. Replacing them is not hard.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Memory returned by dma_alloc_coherent() should already be zeroed
out, so there's no need to do this explicitly.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Use the potentially endianness-changing readl, writel and siblings
directly. They looks prettier and are the correct thing to do, as
even if the CPU is in big-endian mode, the peripherals are little-endian.
Unlike Linux, barebox readl,writel are the same Linux'
{readl,writel}_relaxed (they don't imply memory barriers)
and thus there shouldn't be any functional change.
Patch was generated by a mass search and replace. I looked it over,
adjust some whitespace and further verified by reviewing the output of
git diff HEAD~1 --word-diff | \
perl -pe 's/\[-(.*?)__raw_/{+$1/; s/-\]\{\+/+}{+/;' \
-e 's/(\{\+.*?\+\})\1/__ALL_IS_WELL__/' | grep '+}{+'
which filters out the common case of lines where a single
__raw_{readT,writeT} had its __raw_ prefix stripped without any
further changes.
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Tested-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The rx buffers must be given to the device initially to work properly.
Otherwise the first packets are corrupted.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Many functions are only used locally but still are globally visible.
Make these function static. Avoids warnings generated with -Wmissing-prototypes
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Linux has phy helpers to access paged registers and to modify phy
registers. Add them to barebox for upcoming realtek phy support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds ethernet support for the Freecale Layerscape SoCs. The
architecture in these SoCs is called "Data Path Acceleration
Architecture" (DPAA). It is comprised of:
- The Queue Manager (QMan)
- Buffer Manager (BMan)
- Frame Manager (FMan)
- Multirate Ethernet Media Access Controller (mEMAC)
The code is based on the corresponding U-Boot driver enriched with
device tree parsing and proper device driver support.
Tested on LS1046a, should work on other SoCs aswell with some minor
quirks. SerDes support has been removed for now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Replace all of the generic PCI boilerplate with device_pci_driver().
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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make local functions static and remove unused code
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This patch backports linux commit e1b505a60366 ("net: phy: micrel: add
125MHz reference clock workaround").
8<--------------------- The original commit message -------------------
net: phy: micrel: add 125MHz reference clock workaround
The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
used as reference clock for the MAC unit. The clock signal must meet the
RGMII requirements to ensure the correct data transmission between the
MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
requirement if the phy is configured as slave. For a complete
describtion look at the errata sheets: DS80000691D or DS80000692D.
The errata sheet recommends to force the phy into master mode whenever
there is a 1000Base-T link-up as work around. Only set the
"micrel,force-master" property if you use the phy reference clock provided
by CLK125_NDO pin as MAC reference clock in your application.
Attenation, this workaround is only usable if the link partner can
be configured to slave mode for 1000Base-T.
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
[m.felsch@pengutronix.de: fix dt-binding documentation]
[m.felsch@pengutronix.de: use already existing result var for read/write]
[m.felsch@pengutronix.de: add error handling]
[m.felsch@pengutronix.de: add more comments]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
8<---------------------------------------------------------------------
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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In dwc_ether_rx(), check the RX descriptor status for various error
conditions. On error, issue a warning with the error status bits and
drop the received frame.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Only the following cdevs do not declare an .lseek() operation:
- Console devices in common/console.c
- Firmware framework in common/firmware.c
- JTAG driver in drivers/misc/jtag.c
- UBI in drivers/mtd/ubi/barebox.c
Of those four, first two are marked DEVFS_IS_CHARACTER_DEV and
implement only .write() operation and the last two don't implement
anything but .ioctl(). While there's probably no meaningful way to use
lseek() against any of those devices, there doesn't seem to be any
harm in allowing it either.
Change devfs_lseek() to ignore absense of .lseek() callback and drop
dev_lseek_default() and all references to it in the codebase.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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If the FEC driver is enabled, but the ethernet device was never
opened due to booting from another source the wait for graceful
transmit stop will always fail. This introduces an unnecessary
boot delay and prints a distracting warning.
As there is no point in trying to shut down the FEC if it was
never started, just skip all of fec_halt in that case.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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While there currently no user of e1000 driver that places those rings
beyond 4GiB boundary, there's also no real reason not to initialize
those registers properly.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Drop explicit "volatile" specifier for struct e1000_rx_desc, "bla"
variable as well as explicit endiannes fix, by using little endian IO
accessors (readl, writel, etc.)
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Consolidate next index calculation code into a helper function and
convert the code to make use of it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Instead of relying on reles of pointer arithmetic (implicit
multiplication by the size of pointer type), change the code to
retreive address of an array elemet to clarify the intent.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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