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path: root/drivers/pci/pci.c
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* PCI: split PCI hierarchy enumeration and config from device registrationLucas Stach2016-11-031-15/+16
| | | | | | | | | | | | | | | This gets rid of some of the special cases in the bus scanning function by splitting hierarchy enumeration and configuration and the actual device registration into 2 passes. This ensures that the PCI hierarchy below a root port is completely set up before any device driver is probed. This simplifies the code and makes it less error prone, while moving the PCI address space layout closer to the one used by Linux. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: align BAR address to BAR sizeLucas Stach2016-11-031-3/+6
| | | | | | | | | PCI BARs require their address to be at least aligned to their size, otherwise address decoding will fail as the base address gets rounded down. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: align address range before scanning bridgeLucas Stach2016-11-031-0/+3
| | | | | | | | Otherwise we may end up with a too low base address and push requests for the upstream bus onto the downstream side. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: only check specific flag for 64bit BARLucas Stach2016-11-031-2/+1
| | | | | | | | The memory type may include other flags, so just check for the 64bit allocation flag to see if the BAR is a 64bit one. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: add some useful debug outputLucas Stach2016-11-031-0/+6
| | | | | | | | This makes diagnosing problems in address space allocation much easier. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: remove bogus host bridge setup skippingLucas Stach2015-06-251-5/+0
| | | | | | | | | | Apparently this was here to fix issues with some QEMU version, but hasn't worked in the intended way for a long time. The probe code should be mature enough by now, so this workaround isn't needed anymore. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: rework BAR size calculationLucas Stach2015-06-251-5/+34
| | | | | | | | | The probe code now does a much better job at detecting bad BARs. Also make sure to preserve any previous content of the BAR registers if we don't relocate them. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: fill in bus primary fieldLucas Stach2015-05-011-0/+1
| | | | | | | | | | | This was erroneously left uninitialzed as nothing was using it. The i.MX6 PCI driver needs this to be filled properly to decide if a config space access is allowed for a specific devfn. This fixes PCI enumeration on the Gateworks GW54xx board. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: register and active bridge device before proceeding to scanLucas Stach2015-05-011-2/+6
| | | | | | | | | | | | The bridge device needs to be registered and activated before the scanning can proceed, as the bridge is the parent for other devices. This fixes a NULL ptr derefernce when scanning PCI hierarchies with bridges behind bridges. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/pci'Sascha Hauer2015-04-131-20/+16
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| * pci: fix copy-paste bugSascha Hauer2015-03-171-1/+1
| | | | | | | | | | | | Test for the correct resource before derefencing it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * pci: Use standard pr_debugSascha Hauer2015-03-171-19/+15
| | | | | | | | | | | | Use pr_debug instead of custom DBG macro. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | pci: make sure to activate devices on the root busLucas Stach2015-04-131-0/+7
|/ | | | | | | | | | | | Commit b8a1bb1dd215 (pci: defer device registration until after bridge setup) changed the activation order of devices, so that bridges above the devices could be configured properly before activating the devices below. This commit failed to acknowledge that there may be devices located directly on the root bus without any bridge in between and so those devices would never get enabled. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* PCI: fix bad bugs in bridge setup codeLucas Stach2015-03-161-2/+4
| | | | | | | | Add the required brackets, so that we don't write unused registers with potentially bogus values. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* sizes.h: move include/sizes.h to include/linux/sizes.hMasahiro Yamada2015-01-081-1/+1
| | | | | | | | | | | | | | This file originates in Linux. Linux has it under include/linux/ directory since commit dccd2304cc90. Let's move it to the same place as well in barebox. This commit was generated by the following commands: find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:' git mv include/sizes.h include/linux/ Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: align bridge windowsLucas Stach2014-11-171-0/+4
| | | | | | | | | | | The bridge filtering logic needs a minimum alignment of 1MB for mem and 4KB for io resources. Take this into account while assigning resources to devices in oredr to not produce overlapping windows between different bridges. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: correct BAR size calculationLucas Stach2014-11-171-3/+3
| | | | | | | | The previous math would return negative sizes for some BARs. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: track parent<->child relationshipLucas Stach2014-10-081-0/+4
| | | | | | | | | So that PCI devices hang down from bridges and root bridges down from the PCI host controller when calling devinfo. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: defer device registration until after bridge setupLucas Stach2014-10-081-1/+5
| | | | | | | | | Otherwise the drivers for a device may probe before the devices parent bridge is fully configured, which leads to errors when accessing the BARs. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: setup bridges and traverse buses behind themLucas Stach2014-10-081-3/+89
| | | | | Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: properly populate prefetchable BARsLucas Stach2014-10-081-14/+45
| | | | | | | | | Some host controllers provide a prefetchable memory area and devices will prefer this for some of their BARs. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: add resource enumLucas Stach2014-10-081-6/+8
| | | | | | | Makes things way clearer than juggling numbers. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: split out device initLucas Stach2014-10-081-63/+74
| | | | | | | To make it reusable and the code more readable. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: set auto-incremented bus numberSebastian Hesselbarth2014-07-311-0/+5
| | | | | | | | | | | | | | | When using more than one PCI bus, we have to assign unique numbers to each bus. Use an auto-incremented bus index and assign it to each registered bus. Also, allow the PCI host controller to update internal registers by calling set_busno with assigned bus number. While at it, add pci_controller struct to set_busno callback, add a back reference to pci_controller to pci_bus, and clean up unused left-overs from Linux import. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: ensure device does ignore BAR manglingSebastian Hesselbarth2014-07-311-0/+5
| | | | | | | | | Disable access to PCI devices I/O and memory regions while mangling BAR registers. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: register device after BAR setupSebastian Hesselbarth2014-07-311-3/+3
| | | | | | | | | | As soon as pci_register_device is called, a potential driver will access its registers. This requires BARs to be set up properly, so move pci_register_device after BAR setup. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: pci_scan_bus: respect 64b BARsSebastian Hesselbarth2014-07-311-1/+11
| | | | | | | | | | | In PCI 64-bit BARs span two 32-bit BARs, therefore if BAR type indicates a 64-bit BAR we have to skip the next BAR register. While at it, also set proper IORESOURCE flags for I/O and 32b MEM. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: pci_alloc_bus(): use xzalloc() instead of kzalloc()Antony Pavlov2014-07-091-8/+8
| | | | | | | | Also drop redundant xzalloc() result check as xzalloc() does not return in case of memory allocation error. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: initial commitAntony Pavlov2014-07-041-0/+292
used shorten version of linux-2.6.39 pci_ids.h Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 04:45:25 +0000