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path: root/drivers/pci/pcie-designware.c
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* PCI: dwc: tune down link up messagesLucas Stach2019-03-071-1/+1
* PCI: dwc: Replace lower into upper case charactersAndrey Smirnov2019-01-081-6/+6
* PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplateAndrey Smirnov2019-01-081-4/+1
* PCI: Fix typos and whitespace errorsAndrey Smirnov2019-01-081-1/+1
* PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() staticAndrey Smirnov2019-01-081-3/+3
* PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specificallyAndrey Smirnov2019-01-081-1/+1
* PCI: dwc: designware: Move _unroll configurations to a separate functionAndrey Smirnov2019-01-081-39/+59
* PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytesAndrey Smirnov2019-01-081-8/+22
* PCI: dwc: all: Modify dbi accessors to take dbi_base as argumentAndrey Smirnov2019-01-081-6/+7
* PCI: dwc: Split pcie-designware.c into host and core filesAndrey Smirnov2019-01-081-381/+5
* PCI: dwc: designware: Fix style errors in pcie-designware.cAndrey Smirnov2019-01-081-12/+12
* PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()Andrey Smirnov2019-01-081-7/+11
* PCI: dwc: all: Split struct pcie_port into host-only and core structuresAndrey Smirnov2019-01-081-92/+105
* PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()Andrey Smirnov2019-01-081-5/+6
* PCI: dwc: all: Rename cfg_read/cfg_write to read/writeAndrey Smirnov2019-01-081-6/+6
* PCI: dwc: designware: Move register defines to designware header fileAndrey Smirnov2019-01-081-72/+0
* PCI: designware: Check for iATU unroll only on platforms that use ATUAndrey Smirnov2019-01-081-5/+5
* PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val argumentsAndrey Smirnov2019-01-081-15/+15
* PCI: designware: Uninline register accessorsAndrey Smirnov2019-01-081-2/+2
* PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()Andrey Smirnov2019-01-081-2/+2
* PCI: designware: Swap order of dw_pcie_writel_rc() reg/val argumentsAndrey Smirnov2019-01-081-23/+23
* PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfacesAndrey Smirnov2019-01-081-2/+2
* PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll()Andrey Smirnov2019-01-081-8/+2
* PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device()Andrey Smirnov2019-01-081-4/+4
* PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs'Andrey Smirnov2019-01-081-5/+5
* PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2Andrey Smirnov2019-01-081-7/+19
* PCI: designware: Check LTSSM training bit before deciding link is upAndrey Smirnov2019-01-081-2/+4
* PCI: designware: Add iATU Unroll featureAndrey Smirnov2019-01-081-11/+90
* PCI: designware: Wait for iATU enableAndrey Smirnov2019-01-081-2/+13
* PCI: designware: Move link wait definitions to .c fileAndrey Smirnov2019-01-081-0/+4
* PCI: designware: Return data directly from dw_pcie_readl_rc()Andrey Smirnov2019-01-081-9/+9
* PCI: designware: Remove incorrect RC memory base/limit configurationAndrey Smirnov2019-01-081-8/+0
* PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()Andrey Smirnov2019-01-081-20/+20
* PCI: designware: Add default link up check if sub-driver doesn't overrideAndrey Smirnov2019-01-081-1/+9
* PCI: designware: Add generic dw_pcie_wait_for_link()Andrey Smirnov2019-01-081-0/+18
* PCI: designware: Explain why we don't program ATU for some platformsAndrey Smirnov2019-01-081-0/+5
* PCI: designware: Make config accessor override checking symmetricAndrey Smirnov2019-01-081-7/+8
* PCI: designware: Simplify control flowAndrey Smirnov2019-01-081-32/+21
* PCI: designware: Ensure ATU is enabled before IO/conf space accessesAndrey Smirnov2019-01-081-0/+8
* PCI: designware: Make "num-lanes" an optional DT propertyAndrey Smirnov2019-01-081-5/+7
* PCI: designware: Require config accesses to be naturally alignedAndrey Smirnov2019-01-081-0/+8
* PCI: designware: Simplify dw_pcie_cfg_read/write() interfacesAndrey Smirnov2019-01-081-14/+13
* PCI: designware: Use exact access size in dw_pcie_cfg_read()Andrey Smirnov2019-01-081-6/+8
* PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASKAndrey Smirnov2019-01-081-1/+1
* PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEMAndrey Smirnov2019-01-081-33/+46
* PCI: designware: Consolidate outbound iATU programming functionsAndrey Smirnov2019-01-081-78/+43
* PCI: imx6: simplify config access codeLucas Stach2015-05-011-9/+2
* pci: Add pcie-designware driverSascha Hauer2015-03-171-0/+564
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