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path: root/drivers/pci/pcie-designware.h
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* PCI: dwc: Constify dw_pcie_host_ops structuresAndrey Smirnov2019-01-081-1/+1
| | | | | | | | | | | | | | | Port of a Linux commit 4ab2e7c0df6b8bbc6c8ea1617b737d33c2510012 The dw_pcie_host_ops structures are never modified. Constify these structures such that these can be write-protected. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Add accessors for write permission of DBIAndrey Smirnov2019-01-081-0/+26
| | | | | | | | | | | | | | | | | | Port of a Linux commit e44abfed6fcb750d24f4438dc9d5a02eebb5fcac The read-only DBI registers can be written only when the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set. Add accessors to enable and disable write permission, and use them instead of accessing MISC_CONTROL_1_OFF directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: designware: Handle ->host_init() failuresAndrey Smirnov2019-01-081-1/+1
| | | | | | | | | | | | | | | | Port of a Linux commit 4a301766f5263dd94c1b95d1b1bbdf338afb1a37 In several dwc-based drivers, ->host_init() can fail, so make sure to propagate and handle this to avoid continuing operation of a driver or hardware in an invalid state. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplateAndrey Smirnov2019-01-081-4/+1
| | | | | | | | | | | | | | | | | Port of a Linux commit 8cfab3cf63cfe5a53e2e566b3b86b30c187edf3a Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license. Remove the boilerplate GPL version 2 language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: Fix typos and whitespace errorsAndrey Smirnov2019-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 96291d565550c1fd363e488cc17cb3189d2e4cc2 Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytesAndrey Smirnov2019-01-081-6/+9
| | | | | | | | | | | | | | | | | | | Port of a Linux commit a509d7d9af5ebf86ffbefa98e49761d813fb1d40 Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: all: Modify dbi accessors to take dbi_base as argumentAndrey Smirnov2019-01-081-4/+15
| | | | | | | | | | | | | | | | | | Port of a Linux commit b50b2db266d8a8c303e8d88590c6416dfe576c6c dwc has 2 dbi address space labeled dbics and dbics2. The existing helper to access dbi address space can access only dbics. However dbics2 has to be accessed for programming the BAR registers in the case of EP mode. This is in preparation for adding EP mode support to dwc driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: Split pcie-designware.c into host and core filesAndrey Smirnov2019-01-081-1/+4
| | | | | | | | | | | | | | Port of a Linux commit feb85d9b1c47ea8dbcae559ff127b433fdb245b7 Split pcie-designware.c into pcie-designware-host.c that contains the host specific parts of the driver and pcie-designware.c that contains the parts used by both host driver and endpoint driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()Andrey Smirnov2019-01-081-1/+0
| | | | | | | | | | | | | | | | Port of a Linux commit 5f334db665173facf2213854408bb5fa2445d0b3 The "num-lanes" DT property is parsed in dw_pcie_host_init(). However num-lanes is applicable to both root complex mode and endpoint mode. As a first step, move the parsing of this property outside dw_pcie_host_init(). This is in preparation for splitting pcie-designware.c to pcie-designware.c and pcie-designware-host.c Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: all: Split struct pcie_port into host-only and core structuresAndrey Smirnov2019-01-081-22/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 442ec4c04d1235f8c664a74004dae54a7a574d18 Keep only the host-specific members in struct pcie_port and move the common members (i.e common to both host and endpoint) to struct dw_pcie. This is in preparation for adding endpoint mode support to designware driver. While at that also fix checkpatch warnings. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Richard Zhu <hongxing.zhu@nxp.com> CC: Lucas Stach <l.stach@pengutronix.de> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Minghuan Lian <minghuan.Lian@freescale.com> CC: Mingkai Hu <mingkai.hu@freescale.com> CC: Roy Zang <tie-fei.zang@freescale.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Niklas Cassel <niklas.cassel@axis.com> CC: Jesper Nilsson <jesper.nilsson@axis.com> CC: Joao Pinto <Joao.Pinto@synopsys.com> CC: Zhou Wang <wangzhou1@hisilicon.com> CC: Gabriele Paoloni <gabriele.paoloni@huawei.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com> For convenience sake, commit c0464062bfea9cd2ef6643d93429eafe8f6c2a4a PCI: dwc: Fix crashes seen due to missing assignments Fix the following crash, seen in dwc/pci-imx6. Unable to handle kernel NULL pointer dereference at virtual address 00000070 pgd = c0004000 [00000070] *pgd=00000000 Internal error: Oops: 805 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.10.0-09686-g9e31489 #1 Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) task: cb850000 task.stack: cb84e000 PC is at imx6_pcie_probe+0x2f4/0x414 ... While at it, fix the same problem in various drivers instead of waiting for individual crash reports. The change in the imx6 driver was tested with qemu. The changes in other drivers are based on code inspection and have been compile tested only. Fixes: 442ec4c04d12 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures") Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> # designware-plat Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> was squashed into this one as well. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: all: Rename cfg_read/cfg_write to read/writeAndrey Smirnov2019-01-081-2/+2
| | | | | | | | | | | | | | | | | No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do anything specific to access configuration space. It can be just renamed to dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Joao Pinto <jpinto@synopsys.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: dwc: designware: Move register defines to designware header fileAndrey Smirnov2019-01-081-0/+78
| | | | | | | | | | | | | | | | | Port of a Linux commmit b90dc392212d1153a12eea15cbc6eae352a3c989 No functional change. Move the register defines and other macros from pcie-designware.c to pcie-designware.h. This is in preparation to split the pcie-designware.c file into designware core file and host-specific file. While at that also fix a checkpatch warning. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-By: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc()Andrey Smirnov2019-01-081-0/+2
| | | | | | | | | | | Export dw_pcie_readl_rc() and dw_pcie_writel_rc(). Many other drivers can use these instead of implementing their own versions. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Swap order of dw_pcie_writel_rc() reg/val argumentsAndrey Smirnov2019-01-081-1/+1
| | | | | | | | | | | | | Port of a Linux commit ad8802189426cf7b3a2ad0444f71981fb81312a8 Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfacesAndrey Smirnov2019-01-081-3/+2
| | | | | | | | | | | | | | | | | | | | Port of a Linux commit 7e00dfd0fbbb2fc276592613f76ded0b9a139a04 The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers allow a driver to override the default DesignWare register accessors. Make the signature of the override functions the same as the default accessors. This makes the default dw_pcie_readl_rc() and the corresponding override more structurally similar: both will compute the final register address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed the address and passed it to the override. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2Andrey Smirnov2019-01-081-0/+1
| | | | | | | | | | | | | | | | Port of a Linux commit fe48cb8538421fbd16ecf8bf95829faf8d8c001e Most of the platforms have 3 or more viewports. For such platforms, We do not need to share viewports between IO and CFG. Assign viewport 2 to IO transactions in such cases. Tested-by: Dong Bo <dongbo4@huawei.com> Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Add iATU Unroll featureAndrey Smirnov2019-01-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit a0601a47053714eecec726aea5ebcd829f817497 Add support for the new iATU Unroll mechanism that will be used from Core version 4.80. The new Cores can support either iATU Unroll or the "old" iATU method, now called Legacy Mode. The driver is perfectly capable of performing well for both. [bhelgaas: split ATU enable timeout to separate patch] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> To avoid breaking i.MX6 PCIE support commit 416379f9ebded501eda882e6af0a7aafc1866700 was squashed here as well PCI: designware: Check for iATU unroll support after initializing host dw_pcie_iatu_unroll_enabled() reads a dbi_base register. Reading any dbi_base register before pp->ops->host_init has been called causes "imprecise external abort" on platforms like ARTPEC-6, where the PCIe module is disabled at boot and first enabled in pp->ops->host_init. Move dw_pcie_iatu_unroll_enabled() to dw_pcie_setup_rc(), since it is after pp->ops->host_init, but before pp->iatu_unroll_enabled is actually used. Fixes: a0601a470537 ("PCI: designware: Add iATU Unroll feature") Tested-by: James Le Cuirot <chewi@gentoo.org> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Move link wait definitions to .c fileAndrey Smirnov2019-01-081-4/+0
| | | | | | | | | | | | | | Port of a Linux commit c388de1c4f0e5da3e96b49efb0388e2a0d34e079 Move the link wait sleep definitions to the .c file as suggested by Jisheng Zhang in a previous patch. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Return data directly from dw_pcie_readl_rc()Andrey Smirnov2019-01-081-2/+1
| | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 446fc23fb6f0cab15011d7daae856091856a65cc dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in space supplied by the caller. Return the u32 value directly instead. This makes the calling code read better and makes it obvious that the caller need not initialize the storage. In the following example it isn't clear whether "val" is initialized before being used: dw_pcie_readl_rc(pp, PCI_COMMAND, &val); if (val & PCI_COMMAND_MEMORY) ... No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Add generic dw_pcie_wait_for_link()Andrey Smirnov2019-01-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of Linux commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32 Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and spear13xx) had similar loops waiting for the link to come up. Add a generic dw_pcie_wait_for_link() for use by all these drivers so the waiting is done consistently, e.g., always using usleep_range() rather than mdelay() and using similar timeouts and retry counts. Note that this changes the Keystone link training/wait for link strategy, so we initiate link training, then wait longer for the link to come up before re-initiating link training. [bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com> NOTE: For some reason, all of the changes to imx6_pcie_wait_for_link() made in 4d107d3b5a686b5834e533a00b73bf7b1cf59df7 are actually not present 886bc5ceb5cc3ad4b219502d72b277e3c3255a32. So there isn't really a kernel commit corresponding to removal of the large comment block or check for !(reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: designware: Simplify dw_pcie_cfg_read/write() interfacesAndrey Smirnov2019-01-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port of a Linux commit 4c45852f494dab827291c656ee9e12f3f4ee64d6 Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to split the address into "addr" and "where". The callees assumed "addr" was 32-bit aligned (with zeros in the low two bits) and they used only the low two bits of "where". Accept the entire address in "addr" and drop the now-redundant "where" argument. As an example, this replaces this: int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) *val = readb(addr + (where & 1)); with this: int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) *val = readb(addr): [bhelgaas: changelog, split access size change to separate patch] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> TODO: Fixup the pcie-designware.h Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* PCI: desginware: Remove bogus prototypesAndrey Smirnov2019-01-081-2/+0
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pci: Add pcie-designware driverSascha Hauer2015-03-171-0/+71
Based on the corresponding kernel driver, only small changes to make it work on barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 05:22:32 +0000