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* mci: core: allocate memory used for DMA with dma_allocHEADmasterAhmad Fatoum24 hours1-6/+6
| | | | | | | | | | | | | | | | | Memory allocated by normal malloc may not fulfill the alignment requirements for DMA. This fixes memory corruption observed on the i.MX8MP when the DMA-enabled eSDHC driver attempts to probe an eMMC. This issues always existed, but only after commit 65ef5d885263 ("ARM64: let 'end' point after the range in cache functions"), the whole 512 bytes were getting invalidated, which corrupted the TLSF malloc header of the block after it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240423060435.1514644-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: imx8mp: sync with Linux v6.9-rc3Ahmad Fatoum43 hours2-35/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sync is mainly done to pull in Linux commit c277ca155d2f0: | Author: Peng Fan <peng.fan@nxp.com> | AuthorDate: Sun Nov 1 19:23:54 2020 +0800 | | clk: imx8m: fix bus critical clk registration | | noc/axi/ahb are bus clk, not peripheral clk. | Since peripheral clk has a limitation that for peripheral clock slice, | IP clock slices must be stopped to change the clock source. | | However if the bus clk is marked as critical clk peripheral, the | assigned clock parent operation will fail. | | So we added CLK_SET_PARENT_GATE flag to avoid glitch. | | And add imx8m_clk_hw_composite_bus_critical for bus critical clock usage | | Fixes: 936c383673b9e ("clk: imx: fix composite peripheral flags") | Reviewed-by: Abel Vesa <abel.vesa@nxp.com> | Reported-by: Abel Vesa <abel.vesa@nxp.com> | Signed-off-by: Peng Fan <peng.fan@nxp.com> | Link: https://lore.kernel.org/r/1604229834-25594-1-git-send-email-peng.fan@nxp.com | Signed-off-by: Stephen Boyd <sboyd@kernel.org> Without this, attempts to reparent e.g. noc_io would hang. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419061003.2590849-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: composite-8m: fix muxing of core and bus clocksAhmad Fatoum43 hours1-11/+15
| | | | | | | | | | | | | | | | | | | | | The i.MX8M differntiates between three types of composite clocks (called slices): Core, Bus and IP (peripheral) clocks. How muxes are configured differs between these clocks, so the driver is populating a mux_ops variable to point at the correct struct clk_ops. Unfortunately, mux_ops wasn't actually used, leading to barebox hangs, depending on the assigned-clock-parents properties in the device tree. This oversight is likely due to the different prototypes of clk_register_composite and clk_hw_register_composite, the latter of which didn't exist when the driver was added. The API is available now, so sync the function with Linux to fix this issue. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419061003.2590849-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx: add IMX_COMPOSITE_CLK_FLAGS_DEFAULT macroAhmad Fatoum43 hours1-2/+5
| | | | | | | | | We use the same flags in two macros and will add one more instance in a follow-up commit, so factor them out into a macro like Linux does. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240419061003.2590849-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx27: add watchdog clockSascha Hauer8 days1-0/+2
| | | | | | | | | Since 87cad17964 the imxwd watchdog driver needs a clock to probe. Add this clock for i.MX27 to make the watchdog driver work again. Fixes: 87cad17964 ("watchdog: imxwd: get and enable clock") Link: https://lore.barebox.org/20240416063126.1345967-2-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* clk: imx27: add nand clockSascha Hauer8 days1-0/+1
| | | | | | | | | The NAND clock is currently missing. The NAND driver doesn't use it currently, but will be using it later once we update the driver. Add this missing clock. Link: https://lore.barebox.org/20240416063126.1345967-1-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: do not copy properties if they already exist in the destinationJonas Richardsen8 days1-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Currently `of_copy_property` copies the given property even if a property with the same name already exists on the destination node. This leads to kernel warnings about duplicate properties: ``` [ 0.014063] Duplicate name in chosen, renamed to "stdout-path#1" [ 0.014093] Duplicate name in chosen, renamed to "bootargs#1" [ 0.014119] Duplicate name in chosen, renamed to "phandle#1" [ 0.014197] Duplicate name in reserved-memory, renamed to "#address-cells#1" [ 0.014226] Duplicate name in reserved-memory, renamed to "#size-cells#1" [ 0.014252] Duplicate name in reserved-memory, renamed to "ranges#1" [ 0.014278] Duplicate name in reserved-memory, renamed to "phandle#1" ``` Therefore, the function was changed to return an error if the property already exists in the destination. The change does not cause any regressions, because the only usage of this function occurs within `arch/arm/boards/raspberry-pi/rpi-common.c` where the original behaviour of the function is obviously unintended. Signed-off-by: Jonas Richardsen <jonasrichardsen@emlix.com> Link: https://lore.barebox.org/20240415122757.327312-1-jonasrichardsen@emlix.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* of: do not acccess 'prop->value' directlyEnrico Scholz8 days1-3/+3
| | | | | | | | | Use of_property_get_value() accessor. Else, wrong results are returned when working with fit images. Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de> Link: https://lore.barebox.org/20240412162925.284747-1-enrico.scholz@sigma-chemnitz.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: core: don't fail MMC probe if HS200 isn't supported in HWAhmad Fatoum8 days1-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | A MMC may support HS200 in theory, but it's unusable due to I/O voltage. Unlike Linux, barebox doesn't check the I/O voltage, so it will attempt enabling HS200 and get told no by the card. This no currently triggered a failure of the probe: mmc1: detected MMC card version 5.0 ERROR: mmc1: mmc_select_hs200 failed, error -5 WARNING: mmc1: Card's startup fails with -5 Cannot set parameter mmc1.probe: I/O error But the correct behavior should be attempting the next speed mode. -EBADMSG is the error code used to indicate this, so return that instead when switching to EXT_CSD_TIMING_HS200 fails, because the card couldn't. This is returned directly as to skip the error message in the err case, which would just be confusing. Fixes: ffa59e16bb96 ("mci: mci-core: add HS200 support") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240415052734.366242-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* soc: rockchip: io-domain: handle missing supply correctlyAhmad Fatoum8 days1-1/+1
| | | | | | | | | | | | | | | The original Linux code calls regulator_get_optional and handles its -ENODEV return code, which morphed into regulator_get when ported to barebox. The error handling stayed as-is leading to causing supplies to trigger errors instead of being silently ignored. As we use NULL to describe the dummy regulator in barebox, we can add a trivial regulator_get_optional implementation and use it to fix the I/O domain driver. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240415053130.368278-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* gpio: rockchip: fix support for RK3588/RK3566Ahmad Fatoum8 days1-1/+15
| | | | | | | | | | | | | | | | | The GPIO controller on newer Rockchip SoCs isn't compatible with the older ones. Back when GPIOv2 support was added, RK3568 was the only SoC supported using it, but since then support for the very similar RK3566 as well as the newer RK3588 has followed, but the driver wasn't extended to support them. As GPIOv2 controllers have an identification register, start checking it like Linux does and use that to detect whether we have a GPIOv2 or GPIOv1. This issue was found trying to read GPIO inputs of the RK3566. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240415053137.368391-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mtd: nand: stm32: fix wrong regmap_bulk_read() usageSascha Hauer8 days1-2/+2
| | | | | | | | | | Compilation of the STM32 NAND driver fails with: error: call to '__regmap_bulk_api_changed' declared with attribute error: Last argument is now number of registers, not bytes. Fix it and include <linux/regmap.h instead Do exactly this to make the driver compile again Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pmdomain: imx8mp-blk-ctrl: fix adb handshake handlingMarco Felsch2024-04-041-6/+22
| | | | | | | | | | | | | | | | | | | | Fix powering the DWC3 USB subsystem which is part of the HSIO BLKCTRL. Currently we enable the USB clocks and the USB module clock within the HSIO BLKCTRL. The later get stuck during the first call of imx8mp_blk_ctrl_power_on() since the parent GPCv2 device is not powered yet. Fix this by porting the Linux imx8mp_blk_ctrl::power_nb notifier_block logic. The Linux driver enable/disable the USB module to propagate the ADB handshake instead of powering it permanently. The logic is executed after the parent GPCv2 power domain is powered so we can access the HSIO BLKCTRL registers. Fixes: 5cb41f0b62dc ("pmdomain: imx: add i.MX8MP HSIO blk-ctrl driver") Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240403153151.2859387-1-m.felsch@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* soc: sifive: l2_cache: fix 32-bit compilationAhmad Fatoum2024-04-031-0/+1
| | | | | | | | | | The StarFive SoCs are 64-bit, but the L2 cache driver could be compile-tested on 32-bit as well. Currently, this would fail, because writeq isn't defined. Fix this by emulating it using a lo-hi write. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240402134501.3689322-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* usb: onboard-hub: bail out if peer hub is already probedLucas Stach2024-04-021-0/+10
| | | | | | | | | | | | | | | Many physical hub chips include multiple logical hubs to handle both USB and 2 and 3. Both logical hubs will then match the onboard hub driver, which means we'll end up with two driver instances trying to control the reset GPIO that is only present once on the physical chip. As this doesn't make sense, just bail out of the probe function when the peer-hub is already probed and can be assumed to handle power, clocks and reset resources of the chip. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.barebox.org/20240327165554.894805-1-l.stach@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dma: Fix compiler warningSascha Hauer2024-04-021-0/+2
| | | | | | | | | | | | of_dma_is_coherent() returns an undefined value on unexpected return values of of_dma_get_coherence(): drivers/of/platform.c: In function 'of_dma_is_coherent': drivers/of/platform.c:128:1: warning: control reaches end of non-void function [-Wreturn-type] This cannot be reached so just add a BUG() to silence the compiler. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: arasan: fix build for non-ZynqMPSteffen Trumtrar2024-04-021-1/+2
| | | | | | | | | Registering sdclk only makes sense on the ZynqMP architecture. Guard calling the function with a IS_ENABLED() Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20240326-worktree-barebox-bosch-be-ppm4-v1-2-7ea75c487348@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: mci-core: fix mci_switch_status callSteffen Trumtrar2024-04-021-3/+1
| | | | | | | | mci_switch_status needs to be called with a boolean instead of a u32. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20240326-worktree-barebox-bosch-be-ppm4-v1-1-7ea75c487348@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* dma: correctly honour dma-noncoherent device tree propertyAhmad Fatoum2024-03-251-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most barebox platforms are either completely cache-coherent with respect to DMA or completely non-coherent. To avoid having to walk the device tree for non-existent dma-coherent and dma-noncohrent properties, barebox thus only does this when CONFIG_OF_DMA_COHERENCY is selected. CONFIG_OF_DMA_COHERENCY is to be selected by platforms that have mixed coherency for DMA masters. Forgetting to select this option can be annoying to debug, which is why devinfo will inform the user of default DMA coherency assignments: DMA Coherent: false (default) In order to allow devinfo to differentiate implicit default and explicit device tree DMA coherency configuration, the struct device::dma_coherent member is not of boolean type, but Instead an enumeration that besides coherent and non-coherent also encodes a DEV_DMA_COHERENCE_DEFAULT state. In practice though, a boolean was saved in this dma_coherent member, leading to any dma-noncoherent property being ignored and the default coherency setting being taken for the node. By fixing the type confusion, we restore working Ethernet on the StarFive JH7100, which is the only SoC we currently support that requires /soc/dma-noncohrent to be set for proper operation of its DMA masters. Fixes: fbdea8fd54fe ("of: populate new device_d::dma_coherent attribute") Reported-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240322142424.981863-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mci: sdhci: replace sdhci_wait_idleSteffen Trumtrar2024-03-188-10/+36
| | | | | | | | | | Linux uses a different sdhci_wait_idle function than what barebox currently does. For HS200 support, the linux version needs to be used. As currently only arasan-sdhci is tested with HS200, keep the old sdhci_wait_idle as sdhci_wait_idle_data and convert all users of it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
* mci: arasan-sdhci: add HS200 tuning support on ZynqMPSteffen Trumtrar2024-03-181-3/+59
| | | | | | | | | | The ZynpMP 8.9a has an Arasan IP core that supports HS200 tuning. Register the callback with the mci-core. Arasan uses the SDHCI tuning method. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: sdhci: add tuning supportSteffen Trumtrar2024-03-182-1/+301
| | | | | | | | | The arasan SDHCI driver doesn't use MMC tuning but SDHCI tuning. Both are not supported yet in barebox. Add SDHCI tuning support from linux v6.7. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: mci-core: replace value with defineSteffen Trumtrar2024-03-181-1/+1
| | | | | | | | Use the newly introduced define for High Speed timing mode instead of just '1'. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: mci-core: add HS200 supportSteffen Trumtrar2024-03-182-10/+254
| | | | | | | | | HS200 is a timing mode for eMMCs to work 8bit with 200MHz clocks. To be used, drivers need to set the correct drive strength, clock phases and then SDHCI can start tuning for HS200. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: core: parse more host capabilities from DTSteffen Trumtrar2024-03-181-6/+30
| | | | | | | | | Port the linux v6.7 mmc host caps2 parsing. While at it, remove the ->no_sd and ->no_sdio. These are bits in the caps2 field. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: arasan: register sdcard/sampleclkSteffen Trumtrar2024-03-181-0/+316
| | | | | | | | Read and register the sampleclk and sdcardclk. They are needed later for HS200 tuning support. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: core: save the set clock as actual_clockSteffen Trumtrar2024-03-181-0/+2
| | | | | | | | Linux mmc_host saves the actual_clock set on the HC. Do the same to use it later. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: arasan: read clk phases from DTSteffen Trumtrar2024-03-181-0/+121
| | | | | | | | Depending on the used SDHCI mode the clock phases are different. Import the helper function to get these values from the DT from linux v6.7. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: arasan: implement 25MHz quirk for zynqmpSteffen Trumtrar2024-03-181-1/+27
| | | | | | | | | | The Arasan on the zynqmp in version 8.9a doesn't meet the timing requirements at 25MHz. It works at 19MHz instead. Add the quirk from linux kernel v6.8-rc4. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
* mci: arasan: fix dma supportSteffen Trumtrar2024-03-181-1/+1
| | | | | | | The last patch accidentally drops the mask in sdhci_wait_for_done. Fixes: b80c0e1ec6 ("mci: arasan: add dma support") Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
* Merge branch 'for-next/misc'Sascha Hauer2024-03-1516-92/+328
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| * net: cpsw: map/unmap buffers used for DMAAhmad Fatoum2024-03-151-18/+28
| | | | | | | | | | | | | | | | | | This doesn't fix any bugs, but it allows CONFIG_DMA_API_DEBUG to check for any future issues that may be introduced. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313175002.3200363-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: cpsw: replace global NetRxPackets with per-interface allocationAhmad Fatoum2024-03-131-1/+7
| | | | | | | | | | | | | | | | | | | | | | NetRxPackets is a remnant of times, where a board had at most one Ethernet controller. This is outdated and we should drop NetRxPackets. Switch over the driver to allocate the receive buffers needed. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313110704.1095554-7-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: ethoc: replace global NetRxPackets with per-interface allocationAhmad Fatoum2024-03-131-1/+9
| | | | | | | | | | | | | | | | | | | | | | NetRxPackets is a remnant of times, where a board had at most one Ethernet controller. This is outdated and we should drop NetRxPackets. Switch over the driver to allocate the receive buffers needed. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313110704.1095554-6-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: gianfar: replace global NetRxPackets with per-interface allocationAhmad Fatoum2024-03-132-7/+13
| | | | | | | | | | | | | | | | | | | | | | NetRxPackets is a remnant of times, where a board had at most one Ethernet controller. This is outdated and we should drop NetRxPackets. Switch over the driver to allocate the receive buffers needed. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313110704.1095554-5-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: enc28j60: replace global NetRxPackets with per-interface allocationAhmad Fatoum2024-03-131-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | NetRxPackets is a remnant of times, where a board had at most one Ethernet controller. This is outdated and we should drop NetRxPackets. The driver doesn't maintain a queue of packets, so let's just allocate it per interface. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313110704.1095554-4-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * net: ep93xx: replace global NetRxPackets with per-interface allocationAhmad Fatoum2024-03-131-3/+13
| | | | | | | | | | | | | | | | | | | | | | NetRxPackets is a remnant of times, where a board had at most one Ethernet controller. This is outdated and we should drop NetRxPackets. The driver already had an unused rx_buffer, so let's make use of it. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313110704.1095554-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of: fdt: justify fdt_machine_is_compatible parsing only the root nodeAhmad Fatoum2024-03-131-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fdt_machine_is_compatible() is a lightweight way to check the top-level compatible without unflattening the DT or pulling in libfdt. The lightness is due to parsing only the root node and looking for the compatible right away. This assumes that no child nodes of the root node precede the compatible property. This is mandated by the specification and dtc throws a syntax error when attempting to violate this. Add a comment referencing the specification to tell future readers why it should be ok for us to assume this. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240313093145.3349370-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: arasan: add dma supportSteffen Trumtrar2024-03-131-7/+9
| | | | | | | | | | | | | | | | Switch from PIO to DMA mode in send_cmd. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Link: https://lore.barebox.org/20240308-v2024-02-0-topic-arasan-dma-support-v1-1-079e10b6ea88@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of: partition: Also add partitions created by addpart to the boot dtbUwe Kleine-König2024-03-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A partition added interactively using addpart was added in of_partition_fixup() before commit aec676b568 ("cdev: record whether partition is parsed from OF"). Restore that behaviour. To do that a new flag DEVFS_PARTITION_FOR_FIXUP is created that behaves very similar what DEVFS_PARTITION_FROM_OF did before. The only difference is that addpart makes use of it (and that stat uses a different string to describe it). Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.barebox.org/20240312100918.604105-1-u.kleine-koenig@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * dma: debug: detect repeated DMA syncAhmad Fatoum2024-03-081-2/+20
| | | | | | | | | | | | | | | | | | | | dma_map_single will do any necessary cache maintenance to make a buffer available to a device. Calling debug_dma_sync_single_for_device on such a buffer is unnecessary, so flag when this happens. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240307170050.3299747-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: add comment about hardcoded 512 bytes for DDRAhmad Fatoum2024-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quoting eMMC 5.1 6.6.24 Dual Data Rate mode operation[1]: After the Device has been enabled for dual data rate operating mode, the block length parameter of CMD17, CMD18, CMD24, CMD25 and CMD56 automatically default to 512 bytes and cannot be changed by CMD16 (SET_BLOCKLEN) command that becomes illegal in this mode. barebox observes this by hardcoding the block length in DDR mode, but a comment would be a welcome addition to explain why. [1]: JESD84-B51, February 2015 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240306184526.627028-1-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of: fdt: implement fdt_machine_is_compatibleAhmad Fatoum2024-03-051-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When finding compatible bootloader spec files, barebox will unflatten each DTB in turn, allocating objects for each property and node, only to compare a single property and then free all the allocations again. Given that this operation is repeated for every device tree until a match is found, it's a good idea to be able to compare machine (top-level) compatibles without having to unflatten the whole FDT. Implemnt fdt_machine_is_compatible() that does just that. This intentionally opencodes the device tree iteration as to minimize code and runtime size. Using libfdt without LTO would be slower and bigger. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240301130445.171385-3-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * of: fdt: factor out FDT header parsingAhmad Fatoum2024-03-041-33/+43
| | | | | | | | | | | | | | | | | | | | Follow-up commit will need to parse the FDT header without unflattening the whole device tree at the same time. Therefore split off the header verification into its own separate function. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240301130445.171385-2-a.fatoum@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: dwcmshc-sdhci: add support for Kalray Coolidge v2 SoC eMMC controllerYann Sionneau2024-03-041-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | Kalray Coolidge v2 SoC eMMC controller needs static tx delay tuning even for basic standard or high speed modes. Add vendor specific callback mechanism for init and implement it for Coolidge v2 SoC. Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com> Link: https://lore.barebox.org/20240301102119.17914-1-ysionneau@kalrayinc.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: sdhci: add register define for P_VENDOR_SPECIFIC_AREAYann Sionneau2024-03-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This register is standardized by SDHCI (See SD Host Controller Simplified Specification v4.20 "1.2 Register Map" and "2.3.14 Pointer Registers to mFFh-100h Area"). It is necessary to access some vendor specific registers for some controllers. Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com> Link: https://lore.barebox.org/20240229155700.17443-3-ysionneau@kalrayinc.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: dwcmshc-sdhci: Fix f_max computationYann Sionneau2024-03-041-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | f_max was possibly set from max-frequency DT property by mci_of_parse() and then overwritten few lines later with the clock frequency, making it impossible to reduce the clock frequency from DT. Move the call to mci_of_parse() after the first assignment to f_max. Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.barebox.org/20240229155700.17443-2-ysionneau@kalrayinc.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mci: dwcmshc-sdhci: Remove superfluous call to sdhci_enable_v4_modeYann Sionneau2024-03-041-2/+0
| | | | | | | | | | | | | | | | | | sdhci_enable_v4_mode is already called from dwcmshc_mci_init which is always called before using the controller from mci-core.c Signed-off-by: Yann Sionneau <ysionneau@kalrayinc.com> Link: https://lore.barebox.org/20240229155700.17443-1-ysionneau@kalrayinc.com Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * input: gpio_keys: only use gpios in poller when not in useSascha Hauer2024-02-231-1/+8
| | | | | | | | | | | | | | Before reading GPIOs in a poller check if they are available. Link: https://lore.barebox.org/20240221142800.1958810-5-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * input: gpio_keys: limit poll rateSascha Hauer2024-02-231-12/+8
| | | | | | | | | | | | | | | | | | GPIOs a sometimes slow to read out, for example when they are provided by I2C GPIO expanders. Limit the poll rate so that we do not slow down barebox more than necessary in these cases. Link: https://lore.barebox.org/20240221142800.1958810-4-s.hauer@pengutronix.de Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 06:30:48 +0000