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* ARM: socfpga: add support for reflex achilles boardSteffen Trumtrar2017-05-041-0/+4
| | | | | Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add arria10 supportSteffen Trumtrar2017-05-031-1/+4
| | | | | | | | | | | | | | | | | | Arria10 is a SoC + FPGA like the Cyclone5 SoCFPGA that is already supported in barebox. Both a the same in some parts, but totaly different in others. Most of the hardware blocks are the same in the SoC parts. The OCRAM is larger on the Arria10 and the SDRAM controller is different. The serial core only supports 32bit accesses (different to the 8bit accesses on the Cyclone5). As Arria10 has 256KB of OCRAM, it is possible to fit a larger barebox (and/or use PBL) instead of the two stage bootprocess used on the Cyclone5 and its 64KB OCRAM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* socfpga: Stop putting 512 byte header on SocFPGA imagesTrent Piepho2016-05-231-1/+1
| | | | | | | | | | | | Since images without the extra header now boot correctly, stop adding it. This makes the image 512 bytes smaller. It also gives the image a correct barebox header. The 512 byte extra header looked like a barebox header (had a "barebox\n" signature) but had incorrect size and text start fields. Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: Makefile.socfpga: fix typoUlrich Ölmann2016-04-271-1/+1
| | | | | Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: socdk: Fix typo in MakefileSascha Hauer2016-03-011-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Terasic DE0-Nano-SoC: add supportTim Sander2016-03-011-0/+8
| | | | | | | | | | | | v7: eof whitespace fixes A Patch for supporting the Terasic DE0 NANO-SoC with barebox. The pretty similar Socrates Board was taken as a starting point with pulling in the memory timings/pinmux from http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign Signed-off-by: Tim Sander <tim@krieglstein.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: socfpga: add Altera SoCFPGA Development Kit supportSteffen Trumtrar2015-03-021-0/+8
| | | | | | | | Add support for the Altera SoCFPGA Development Kit. The setup is based on the GHRD from Altera. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: socfpga: Do not pollute Make variable namespaceSascha Hauer2013-11-221-6/+6
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: SoCFPGA: Add EBV SoCrates board supportSascha Hauer2013-09-231-0/+8
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: SoCFPGA: Add Terasic SoCkit board supportSascha Hauer2013-09-231-0/+7
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Add Altera SoCFPGA supportSascha Hauer2013-09-231-0/+19
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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