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Add support for the Xilinx Zynq UltraScale+ MPSoC ZCU106 evaluation
board.
The changes are derived from the ZCU104 board support by applying
s/104/106/g (more or less).
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.barebox.org/20210913121350.9307-2-michael.riesch@wolfvision.net
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP)
and the Xilinx ZCU104 board.
Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL)
already took care of initializing the RAM. Also for debug_ll, the UART
is expected to be already setup correctly. Thus, you have to add the
Barebox binary to a boot image as described in "Chapter 11: Boot and
Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual".
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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