| Commit message (Collapse) | Author | Age | Files | Lines |
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Since the commit
5a1a5ed2537d7d12f851f3778707681d6c08d6e8
ARM: images: use piggydata
the loading mechanism in the arria10 xload is neither functional nor needed.
Now, barebox has/can be loaded like a normal image, so the filesize, that is
written to the barebox header, can be evaluated.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for building a barebox image that boots with the
Linux ARM Kernel booting convention. Support for this image can be
enabled in Kconfig. It picks up a device tree passed in r2. This new
image helps for example with qemu. It can be started with:
qemu-system-aarch64 -m 2G -M virt -kernel images/barebox-dt-2nd.img -cpu cortex-a57 -serial stdio
or:
qemu-system-arm -m 1G -M sabrelite -kernel images/barebox-dt-2nd.img -nographic -dtb arch/arm/dts/imx6q-sabrelite.dtb
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Ignore the new image files with .pimximg and .psimximg extensions and
the sha256 sum files.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Both STM32MP BootROM and TF-A first stage expect subsequent bootloader
stages to feature a specific STM32 file header. Generate this image
type by default.
If for some reason, the image without stm32 header is required, the
start_stm32mp157c_dk2.pblb can be used.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Both STM32MP BootROM and TF-A first stage expect subsequent bootloader
stages to feature a specific STM32 file header. Add a stm32image
utility to address this.
Signed-off-by: Marco Felsch <marco.felsch@gmail.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The arch was renamed to stm32mp, so it doesn't look out of place when
the stm32mp2 is released. Fix spotted comments/labels with the old
name. While at it, fix a typo about the SoC name on the DK2 board.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Rework the evk boot flow to use the new piggydata load function and
install a trampoline for the TF-A setup. This allows the PBL boot
process to stay in SRAM up until the verification of the piggydata is
done and main barebox can be loaded.
The trampoline loads 4 bytes right after the trampoline, we copy the
runtime offset there so the trampoline jumps back into the SRAM PBL.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Create a sha256sum of the compressed barebox image and always add it to
the PBL. We also add a custom linker section for ARM, to retrieve the
sha256sum for piggydata verification.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Implement signing of the PBL for i.MX8MQ.
The imagesize is also modified to i.MX8MQ to only contain the PBL.
This obsoletes the max_load_size, which is kept for other boards
currently using it.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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- switch the i.MX1 based scb9328 board to device tree
- Remove scb9328_defconfig and enable scb9328 board support in
imx_defconfig
- Remove old environment and switch to new default environment
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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To prepare for addition of another ZII i.MX7D based board, i.MX7D
RMU2, rename zii-imx7d-rpu2 to zii-imx7d-dev to avoid any image naming
confusion.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Other images/Makefile.${arch}s, e.g. images/Makefile.imx, populate
pblp-* with the entry points to build, not the pbl file that's
generated. Adjust the images/Makefile.stm32mp to do the same.
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Serial and clk driver both depend on CONFIG_ARCH_STM32MP1,
so either the Kconfig symbol or their depend needs to change.
Patches posted by the vendor to Linux, U-Boot and their BSP
Yocto-Layer speak of a STM32MP-Family of which the STM32MP1
is the first series, thus rename the arch by dropping the 1.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The results are bytewise identical apart from armada-xp-db where the
(AFAIK unused) parameters for the binary header are different (i.e.
0000005b 00000000 instead of 0000005b 00000068 for all other boards).
The advantage is that the build system now knows about the binary
headers and changes to them result in a rebuild of the images.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add a phyCORE-i.MX 6ULL with eMMC. It has following features:
- i.MX 6ULL Y2 792 MHz
- 512 MB RAM
- 4 GB eMMC
- 10/100 MBits Ethernet
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Prepare for the new phyCORE-i.MX 6UL/ULL eMMC module by extending the
dts filenames by their boot medium. Also add the boot medium to the
compatible to be able to perform boot medium dependent setup code.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The phyCORE-i.MX 6Solo/DualLight is available with low-cost and
full-featured phyBOARD-Mira. One crucial difference is the supported
max. ethernet speed. On the full-featured Mira it is 1000 MBit/s but on
the low-cost Mira it is only 100 MBit/s. To cover this difference two
different images are necessary for low-cost and full-featured. Thus a
low-cost variant is added for the phyCORE-i.MX 6Solo with NAND and the
phyCORE-i.MX 6 DualLight with eMMC.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The csfbin files are created during a HABV4 build, ignore them since they
are automatically generated.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Starting with commit 5a1a5ed2537d ("ARM: images: use piggydata") this file type
is not known anymore, so clean up.
Signed-off-by: Ulrich Ölmann <u.oelmann@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add support for the Digi CCIMX6UL SBC Pro.
It is based on the Digi CCIMX6UL SOM with 256MB RAM and 256MB NAND
flash.
v2:
- fix includes
- rename folder to som
- switch to compressed dtb
- remove the unnecessary get_runtime_offset
all from Ahmad Fatoum
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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We have to build correct images suitable for QSPI, thus have to call
lspbl_spi_image instead of lspbl_image. In lowlevel code call the
xload function which detects the bootsource rather than hardcoding
SD/MMC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This unifies the two different pbi files. With our approach for QSPI
booting differences in the pbi files are not necessary:
- We do not do execute in place for QSPI, so we do not need different
image execution addresses
- Setting up the QSPI clock doesn't hurt even for SD boot
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.
The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.
U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.
Lines like this should be removed:
09550000 000f400c
This sets the binary execution address:
09570604 40100000
For barebox it should be changed to 0x10000000.
As a result the PBI files can probably be unified between SD and QSPI
boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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TQ has unified SD and eMMC images in their U-Boot. Do the same in
barebox aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds initial STMicroelectronics MP1 support along with support
for the DK2 devel board. Only very basic support:
- UART
- SDRAM memory base/size
- No 1st stage support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the TQ TQMLS1046a board. Currently supported:
- UART
- SD/MMC
- Network on eth3, eth2 currently not working for unknown reasons
First stage support exists but is currently untested. Serdes ports are
not yet supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The RDB is the Freescale LS1046a reference board. This patch adds
support for it. Currently supported:
- DDR4 RAM as read from SPD EEPROM
- UART
- SD/MMC
- RGMII network ports
The Serdes ports are currently not supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds basic Layerscape support:
- Makefile/Kconfig
- Register maps
- errata workarounds
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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PBL images are often constrained in size by limitations exposed by
the SoCs SRAM size or partition sizes on the boot device. So far
we tried to configure these limits in Kconfig, but with PBL multi
images and thus different limitations for the different supported
images this no longer works. This patch has another approach for
it:
During build time make variables containing the relevant sizes for
each image are created. These are:
PBL_CODE_SIZE_$(symbol)
PBL_MEMORY_SIZE_$(symbol)
PBL_IMAGE_SIZE_$(symbol)
PBL_CODE_SIZE_$(symbol) contains the pure code size of the PBL, it
should be smaller than the available SRAM during boot. Normally the
PBL's bss segment also needs to be in the initial SRAM, for this
case PBL_MEMORY_SIZE_$(symbol) is the relevant variable.
PBL_IMAGE_SIZE_$(symbol) contains the full size of the PBL image
including the compressed payload (but without any image headers
created later by SoC specific image tools).
$(symbol) is a placeholder for the start symbol used for this PBL image,
thus for the i.MX53 QSB with entry start_imx53_loco
PBL_CODE_SIZE_start_imx53_loco
will be created. The images/Makefile.* can use these variables directly
to check sizes or specify the same variables with a "MAX_" prefix. So
when images/Makefile.imx specifies
MAX_PBL_CODE_SIZE_start_imx53_loco = 0x10000
then the build system will make sure that the PBL code for the QSB will
not get bigger than 64KiB.
Also included in this patch are the size restrictions for the i.MX8MQ
images as an example how to use this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Add new grouping comments for vf6xx- and Cortex-A7 based i.MX6 boards.
Sort moved entries alphabetically.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Compute Module needs "no-sd" property on the MMC interface otherwise
mci-bcm2835 hangs on SD card probe.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For platforms such as the at91, the boot ROM imposes an upper limit
on barebox file size. Prior to 5a1a5ed253 ("ARM: images: use piggydata"),
BAREBOX_MAX_PBLX_SIZE seems to have been the way to go for limiting
the size of the final barebox binary when using the PBL.
With pblx removed, this variable is of no use, so have the existing
BAREBOX_MAX_IMAGE_SIZE replace its functionality.
Currently BAREBOX_MAX_IMAGE_SIZE is only checked against in the non-PBL
case, so add a check in the PBL case as well.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The phyCORE-i.MX8M aka PCL-066 is a SoM containing a i.MX8M SoC.
phyCORE-i.MX8M:
- 1GB LPDDR4 RAM
- eMMC
- microSD
- Ethernet
Signed-off-by: Christian Hemp <christian.hemp@posteo.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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At least some ath79 SoC have build in 32K RAM. It allow us to use
lowlevel portion of barebox to bootstrap the system by using JTAG
debugger (For example OpenOCD).
Since ath79 has no reliable way to stop the CPU execution before
reading SPI Flash, this can cause different issues. To avoid it, we
need to flash a execution trap with software debug breakpoint to the
flash.
The workflow should be as follow:
- After power on or reset the CPU will start execution of SPI flash.
As soon as software debug breakpoint is executed, CPU will halt and
notify OpenOCD about breakpoint event.
- OpenOCD will load reduced barebox to SRAM and execute it.
This part will do all needed low level initialization - PLL, RAM and
trigger second breakpoint event.
- OpenOCD will load full barebox version to the main RAM and start
execution.
It can be used for bring-up, so no regular flashing is needed.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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