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* ARM: Layerscape: TQMLS1046a: Support booting from QSPISascha Hauer2019-05-101-2/+2
| | | | | | | | | We have to build correct images suitable for QSPI, thus have to call lspbl_spi_image instead of lspbl_image. In lowlevel code call the xload function which detects the bootsource rather than hardcoding SD/MMC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: unify pbi filesSascha Hauer2019-05-101-2/+2
| | | | | | | | | | | This unifies the two different pbi files. With our approach for QSPI booting differences in the pbi files are not necessary: - We do not do execute in place for QSPI, so we do not need different image execution addresses - Setting up the QSPI clock doesn't hurt even for SD boot Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: Add QSPI boot supportSascha Hauer2019-05-101-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting Layerscape from QSPI is a bit tricky and the approach we take is different from the one U-Boot has taken, so it's worth writing and reading the following explanation. The QSPI controller can map the Flash contents into the memory space (On LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this memory window. The Layerscape SoCs have a PowerPC history, so it seemed appropriate for the designers to let the QSPI controller operate in big endian mode by default. To let the SoC see the correct RCW we have to write the RCW and PBI data with be64 endianess. Our PBL image tool pokes the initial binary into the SoC internal SRAM using PBI data as done with SD/MMC boot aswell. barebox then changes the QSPI controller endianess to le64 to properly read the barebox binary (placed at an flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and jumps to it. U-Boot has another approach. Here the initial binary is executed in place directly at 0x40100000. This means the QSPI controller endianess must be swapped inside the PBI data. This has the effect that the whole RCW/PBI data must be 64bit endianess swapped *except* the very last word of the PBI data which contains the CRC command and is read already with changed endianess. As a conclusion when porting QSPI PBI files from U-Boot to barebox skip commands changing the endianess in the QSPI controller and make sure the image is executed in internal SRAM and not in the Flash memory window. Lines like this should be removed: 09550000 000f400c This sets the binary execution address: 09570604 40100000 For barebox it should be changed to 0x10000000. As a result the PBI files can probably be unified between SD and QSPI boot. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: Layerscape: TQMLS1046a: Unify SD and eMMC imagesSascha Hauer2019-05-081-6/+1
| | | | | | | TQ has unified SD and eMMC images in their U-Boot. Do the same in barebox aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/stm32'Sascha Hauer2019-04-092-0/+9
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| * ARM: Add initial STM32MP1 supportSascha Hauer2019-03-132-0/+9
| | | | | | | | | | | | | | | | | | | | | | This adds initial STMicroelectronics MP1 support along with support for the DK2 devel board. Only very basic support: - UART - SDRAM memory base/size - No 1st stage support Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/layerscape'Sascha Hauer2019-04-083-1/+96
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| * | ARM: Layerscape: Add TQ TQMLS1046a board supportSascha Hauer2019-03-131-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the TQ TQMLS1046a board. Currently supported: - UART - SD/MMC - Network on eth3, eth2 currently not working for unknown reasons First stage support exists but is currently untested. Serdes ports are not yet supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Layerscape: Add LS1046a RDB board supportSascha Hauer2019-03-131-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RDB is the Freescale LS1046a reference board. This patch adds support for it. Currently supported: - DDR4 RAM as read from SPD EEPROM - UART - SD/MMC - RGMII network ports The Serdes ports are currently not supported. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: Add basic Layerscape supportSascha Hauer2019-03-132-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic Layerscape support: - Makefile/Kconfig - Register maps - errata workarounds Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | pbl multiimage: Allow to check image sizesSascha Hauer2019-03-132-0/+35
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PBL images are often constrained in size by limitations exposed by the SoCs SRAM size or partition sizes on the boot device. So far we tried to configure these limits in Kconfig, but with PBL multi images and thus different limitations for the different supported images this no longer works. This patch has another approach for it: During build time make variables containing the relevant sizes for each image are created. These are: PBL_CODE_SIZE_$(symbol) PBL_MEMORY_SIZE_$(symbol) PBL_IMAGE_SIZE_$(symbol) PBL_CODE_SIZE_$(symbol) contains the pure code size of the PBL, it should be smaller than the available SRAM during boot. Normally the PBL's bss segment also needs to be in the initial SRAM, for this case PBL_MEMORY_SIZE_$(symbol) is the relevant variable. PBL_IMAGE_SIZE_$(symbol) contains the full size of the PBL image including the compressed payload (but without any image headers created later by SoC specific image tools). $(symbol) is a placeholder for the start symbol used for this PBL image, thus for the i.MX53 QSB with entry start_imx53_loco PBL_CODE_SIZE_start_imx53_loco will be created. The images/Makefile.* can use these variables directly to check sizes or specify the same variables with a "MAX_" prefix. So when images/Makefile.imx specifies MAX_PBL_CODE_SIZE_start_imx53_loco = 0x10000 then the build system will make sure that the PBL code for the QSB will not get bigger than 64KiB. Also included in this patch are the size restrictions for the i.MX8MQ images as an example how to use this. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: Makefile.imx: group and sort board entriesAlexander Kurz2019-03-271-53/+55
|/ | | | | | | | Add new grouping comments for vf6xx- and Cortex-A7 based i.MX6 boards. Sort moved entries alphabetically. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi'Sascha Hauer2019-03-071-1/+5
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| * ARM: rpi: Add device tree for Compute Module 3.Tomaz Solc2019-02-191-1/+5
| | | | | | | | | | | | | | Compute Module needs "no-sd" property on the MMC interface otherwise mci-bcm2835 hangs on SD card probe. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/misc'Sascha Hauer2019-03-071-0/+1
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| * | images: pbl: verify CONFIG_BAREBOX_MAX_IMAGE_SIZE is not exceededAhmad Fatoum2019-03-071-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | For platforms such as the at91, the boot ROM imposes an upper limit on barebox file size. Prior to 5a1a5ed253 ("ARM: images: use piggydata"), BAREBOX_MAX_PBLX_SIZE seems to have been the way to go for limiting the size of the final barebox binary when using the PBL. With pblx removed, this variable is of no use, so have the existing BAREBOX_MAX_IMAGE_SIZE replace its functionality. Currently BAREBOX_MAX_IMAGE_SIZE is only checked against in the non-PBL case, so add a check in the PBL case as well. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: phyCORE-i.MX8M SOM supportChristian Hemp2019-02-251-0/+5
|/ | | | | | | | | | | | | | The phyCORE-i.MX8M aka PCL-066 is a SoM containing a i.MX8M SoC. phyCORE-i.MX8M: - 1GB LPDDR4 RAM - eMMC - microSD - Ethernet Signed-off-by: Christian Hemp <christian.hemp@posteo.de> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mips'Sascha Hauer2019-02-131-0/+8
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| * MIPS: ath79: add spi and sram bootstrap helpersOleksij Rempel2019-01-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least some ath79 SoC have build in 32K RAM. It allow us to use lowlevel portion of barebox to bootstrap the system by using JTAG debugger (For example OpenOCD). Since ath79 has no reliable way to stop the CPU execution before reading SPI Flash, this can cause different issues. To avoid it, we need to flash a execution trap with software debug breakpoint to the flash. The workflow should be as follow: - After power on or reset the CPU will start execution of SPI flash. As soon as software debug breakpoint is executed, CPU will halt and notify OpenOCD about breakpoint event. - OpenOCD will load reduced barebox to SRAM and execute it. This part will do all needed low level initialization - PLL, RAM and trigger second breakpoint event. - OpenOCD will load full barebox version to the main RAM and start execution. It can be used for bring-up, so no regular flashing is needed. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2019-02-131-0/+10
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| * | ARM: i.MX: Add support for ZII i.MX8MQ based devicesAndrey Smirnov2019-02-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the following ZII i.MX8MQ based boards: - ZII i.MX8MQ RMB3 - ZII i.MX8MQ Zest Most of the basic peripherals are supported by this patch. More advanced features such as PCIe, display support, etc, are planned to be added later. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | ARM: imx: add support for Udoo Neo fullUwe Kleine-König2019-01-181-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | Original patch from Uwe Kleine-König, I fixed the review comments and the imxcfg file to use the udoo neo values. I also tested the support on the udoo neo full board. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / Revert "images: Drop unnecessary fix_size"Sascha Hauer2019-02-131-1/+2
|/ | | | | | | | | | | | | This reverts commit 5c0e16591d9471a345b77a41fde76de34f301f6b. The fix_size scripts is not necessary for newer ARM toolchains, it is however necessary for the older ARM toolchains (gcc-5 and older). The original reason to drop fix_size was that it doesn't work on MIPS. With this patch we add the -i flag so that we ignore unknown images and can succesfully build MIPS images. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: check for use of obsolete pblx-*Ahmad Fatoum2019-01-181-0/+4
| | | | | | | | | | | | | | pblx-* has been removed in 5a1a5ed253 ("ARM: images: use piggydata") and using it (e.g. because a patchset was rebased) results in a non-obvious: make[1]: *** No rule to make target 'images/*.pblx.*', \ needed by 'images/barebox-*.img'. Stop. Avoid this by explicitly failing with an error message whenever pblx-y or pblx- has been defined. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: pblx is now pblbSascha Hauer2019-01-181-1/+1
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* images: Drop unnecessary fix_sizeSascha Hauer2019-01-161-2/+1
| | | | | | | | Now that we compile the compressed binary into the decompressor we no longer need fix_size but can use the linker to fill in the image size into the binary. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/ultrascale'Sascha Hauer2019-01-152-0/+9
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| * ARM: zynqmp: add support for Xilinx ZCU104 boardMichael Tretter2018-12-102-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Xilinx Zynq Ultrascale+ MPSoC architecture (ZynqMP) and the Xilinx ZCU104 board. Barebox is booted as BL33 in EL-1 and expects that a BL2 (i.e. the FSBL) already took care of initializing the RAM. Also for debug_ll, the UART is expected to be already setup correctly. Thus, you have to add the Barebox binary to a boot image as described in "Chapter 11: Boot and Configuration" of "Zynq Ultrascale+ Device Technical Reference Manual". Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/mips'Sascha Hauer2019-01-158-2/+47
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| * | MIPS: port all mach* to multiimageOleksij Rempel2018-12-177-1/+46
| | | | | | | | | | | | | | | Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | images: piggy: use "a" instead of #alloc flagOleksij Rempel2018-12-131-1/+1
| |/ | | | | | | | | | | | | | | "#alloc" is not working with MIPS compiler. The "a" variant seems to be more generic and works with ARM and MIPS. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/kconfig'Sascha Hauer2019-01-151-2/+0
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| * | kbuild: add .SECONDARY special targetMasahiro Yamada2019-01-031-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the following Linux commits: - 54a702f70589 ("kbuild: mark $(targets) as .SECONDARY and remove .PRECIOUS markers") - 8e9b61b293d9 ("kbuild: move .SECONDARY special target to Kbuild.include") This consolidates those two commits and adjusts commit log for barebox. GNU Make automatically deletes intermediate files that are updated in a chain of pattern rules. Example 1) %.dtb.o <- %.dtb.S <- %.dtb <- %.dts Example 2) %.o <- %.c <- %.c_shipped arch/arm/crypto/Makefile marks such targets as .PRECIOUS to prevent Make from deleting them, but the correct way is to use .SECONDARY. .SECONDARY Prerequisites of this special target are treated as intermediate files but are never automatically deleted. .PRECIOUS When make is interrupted during execution, it may delete the target file it is updating if the file was modified since make started. If you mark the file as precious, make will never delete the file if interrupted. Both can avoid deletion of intermediate files, but the difference is the behavior when Make is interrupted; .SECONDARY deletes the target, but .PRECIOUS does not. The use of .PRECIOUS is relatively rare since we do not want to keep partially constructed (possibly corrupted) targets. .SECONDARY with no prerequisites causes all targets to be treated as secondary. This agrees the policy of Kbuild. scripts/Kbuild.include seems a suitable place to add it because it is included from almost all sub-makes. I deleted 'SECONDARY' (no dot) from images/Makefile, which I guess a typo. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/imx'Sascha Hauer2019-01-151-3/+12
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| * | | ARM: CCMX51: Switch to multiimage supportAlexander Shiyan2019-01-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a cumulative patch for the Digi ConnectCore CCMX51 SOM. It includes: - Switch board to devicetree probe. - Add MMC update handler. - Switch to multiimage support. - Cleanup and optimize board code. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | phycard-imx27: add support for 64MB RAM variantsBaeuerle, Florian2018-12-101-3/+7
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Some older pca100 boards were available with 64MB RAM. The chips require a slightly different sdram controller initialization. Support this by building bootloader images for both variants. Signed-off-by: Florian Bäuerle <florian.baeuerle@allegion.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'for-next/am35xx'Sascha Hauer2019-01-152-0/+25
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| * | ARM: omap: Add board support for WAGO pfc200 platformSascha Hauer2019-01-072-0/+25
| |/ | | | | | | | | | | This adds support for the AM3517 based WAGO pfc200 SPS. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | images: fix force rebuild of piggy.oSam Ravnborg2019-01-031-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | piggy.o would be build for every time barebox was built This had the sideeffect that the image(s) would always be rebuilt despite no changes Fix this by adding piggy.o to targets and avoid an extra command in the rule to create .pblb files The patch includes the removal of a stray assignment Fixes: 5a1a5ed253 ("ARM: images: use piggydata") Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Images: Add image size to built imagesSascha Hauer2018-12-181-0/+1
|/ | | | | | | | | | | This brings back the image size written into the built images which got lost in the conversion to using piggydata in the PBL images. Fixes: 5a1a5ed253 ("ARM: images: use piggydata") Reported-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Teresa Remmet <t.remmet@phytec.de>
* ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULLStefan Riedmueller2018-12-061-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phyCORE-i.MX 6ULL now comes in a full featured (Y2 variant) and a low cost (Y0 variant) version. The main difference for the barebox is the missing second USB OTG port on the Y0 variant and the RAM configuration. So to account for these differences the existing low cost version is renamed and the full featured version added. The results are following phyCORE-i.MX 6ULL modules: phyCORE-i.MX 6ULL low cost: - i.MX 6ULL Y0 - 256 MB RAM - NAND - Ethernet 10/100 MBits - USB OTG phyCORE-i.MX 6ULL full featured: - i.MX 6ULL Y2 - 512 MB RAM - NAND - Ethernet 10/100 MBits - USB OTG - USB Host Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: images: use piggydataSascha Hauer2018-12-0314-545/+521
| | | | | | | | | | | | | | | | | | | | | | | | | | The way we assemble the multi images on ARM is rather complicated and error prone. We currently cat the compressed barebox image behind the PBL executable and need some magic to obtain the size of the payload and also have to do tricks to reliably get a pointer to the compressed image. This patch switches over to compile the compressed payload into the PBL image itself which has proven to work for the single PBL case and for the ARM Linux Kernel aswell. The goal is to unify the single PBL and the multi PBL cases together in the future to get an easier startup path for ARM. This patch has been tested on the i.MX53 QSB, i.MX53 Vincell, Beaglebone black (both MLO and 2nd stage) and a Phytec phyFLEX i.MX6 board. SoCFPGA Arria10 has also be changed slightly with this patch. We used to generate a single image (barebox-socfpga-achilles.img) which was used as xload image and full image. We now instead generate two images: barebox-socfpga-achilles-xload.img and barebox-socfpga-achilles.img, the former loaded by the ROM and the latter loaded by the xload image. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX: GuF Vincell: Use DCD table to setup SDRAMSascha Hauer2018-11-301-10/+4
| | | | | | | | | This patch removes the xload mechanism to configure SDRAM and instead installs a DCD table. The DCD table has been generated from the FSL DDR3 script aid Excel sheet (version 0.0.1). The calibration values were taken from a calibration run with the barebox internal functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/rpi3'Sascha Hauer2018-11-091-0/+4
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| * ARM: rpi: add raspberry pi 3 supportLucas Stach2018-11-051-0/+4
| | | | | | | | | | | | | | | | | | This adds basic support at the same feature level as the other supported raspberry pi boards. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Roland Hieber <r.hieber@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | Merge branch 'for-next/imx'Sascha Hauer2018-11-091-0/+10
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| * | ARM: i.MX: Add liteboard supportMarcin Niestroj2018-11-091-0/+10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | liteboard is a development board which uses liteSOM as its base. liteSOM can't exist on its own, but is used as part of other boards - it only contains processor and memory. Hardware specification: * liteSOM: - i.MX6UL - 256M or 512M DDR3 RAM - eMMC (uSDHC2) * Ethernet PHY * USB host (usb_otg1) * MicroSD slot (uSDHC1) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* / ARM: at91: Add initial support for the EVB-KSZ9477 eval boardAhmad Fatoum2018-11-051-0/+4
|/ | | | | | | | | | | | The EVB-KSZ9477 is an evaluation board for the KSZ9477 ethernet switch. This board is equipped with a atsama5d3 SoC with 256MiB of SDRAM, 256MiB of NAND flash and a SD card slot. For now only second stage booting is supported with AT91bootstrap as first stage loader. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX: Add support for ZII's i.MX7D-based RPU2 boardAndrey Smirnov2018-10-081-0/+5
| | | | | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'for-next/mxs'Sascha Hauer2018-09-111-0/+8
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