barebox - barebox master repository

	Commit message (Collapse)	Author	Age	Files	Lines
*	PCI: imx6: Add proper i.MX6+ reset sequence	Andrey Smirnov	2016-04-28	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	I.MX6+ version of the silicon exposed PCIe core's reset signal as a bit in one of the control registers. As a result using old, pre-i.MX6+, reset sequence on i.MX6+ leads to Barebox hanging during startup. Using exposed reset bit instead solves the problem. This commit is based on portions of commit c34068d48273e24d392d9a49a38be807954420ed in http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	pci: Add i.MX6 pcie support	Sascha Hauer	2015-03-17	1	-0/+8
\| \| \| \| \| \| \|	Based on the corresponding kernel driver with changes to make it work on barebox. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority	Sascha Hauer	2014-03-29	1	-0/+18
\| \| \| \| \| \| \| \| \| \|	This is needed so that the IPU framebuffer scanout cannot be starved by VPU or GPU activity. Some boards like the SabreLite and SabreSD seem to set this in the DCD already, but the documented register reset values do not contain the necessary settings. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	ARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and IPU1/2_MUX	Philipp Zabel	2014-03-19	1	-8/+8
\| \| \| \| \|	Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
*	mfd: Add i.MX6 iomux gpr header file	Sascha Hauer	2012-12-07	1	-0/+320
	Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>