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This adds the DDR driver for the i.MX8MQ/i.MX8MM. It's taken from
U-Boot v2020.04-rc1 with slight modifications for barebox
The i.MX8MQ boards in the tree currently use the output of an earlier
version of the NXP i.MX8M DDR Tool which doesn't use a controller driver
but instead does most stuff in board code. It seems this can coexist
with the new driver, only a few helper functions that previously lived
in arch/arm/mach-imx/imx8-ddrc.c are now provided by the new driver.
Tested on an i.MX8MM EVK
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds support for the pll14xx found on i.MX8MM devices. This is
taken from the Kernel as of v5.5. Since we'll need some early setup
for the PLL a PBL hook is added to be called from lowlevel code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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For boards that do the RAM setup in code we can up to now only download
the PBL part to SRAM. This patch adds support for downloading the rest
of the image after the RAM has been configured.
The ROM is nice enough to leave the USB controller initialized after a
download, so we don't have to reinitialize it, but can simply continue to
use the controller. Like all two-staged loading processes on i.MX this
needs board support, it will only work when a board calls
imx_barebox_load_usb() or one of the SoC specific variants.
This needs the host counterpart in imx-usb-loader which is done in the
next patch.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The register definitions will be shared by the regular and the
pbl driver, so move them to a header file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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struct ccsr_qman is ifdeffed for different versions of this structure.
CONFIG_SYS_FSL_QMAN_V3 is not defined which means we happen to use
the wrong version on LS1046a. Hardcode it to the v3 version to make
it work on LS1046a and rename it to ccsr_qman_v3 to make it obvious
that it needs a change on non v3 versions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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include/soc/fsl/fsl_qbman.h contains function prototypes we do not
implement, drop them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The icid tables are generated with several macros which makes the code
hard to read. Drop the macros.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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edev->halt is implemented, but not called by the core during shutdown.
We have to call it manually during device remove. With this and also
resetting the whole FMan during shutdown the driver now works properly
when started second stage from another barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds driver support for the 12 GPIO banks on the STM32MP157.
As they are accessible to both the Cortex-A cores as well as the Cortex-M
core, modifications to these are protected by a hardware spinlock
and clocks are enabled/disabled as required.
All register fiddling done by the driver is collected in <soc/stm32/gpio.h>,
so future PBL code may make use of it as well to chainload barebox proper.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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fsl_ddr_set_memctl_regs() is not only used internally in the DDR
controller driver, but can also be called by the boards to configure
a static setting. Move the prototype to include/ where it can be
used by board code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds basic Layerscape support:
- Makefile/Kconfig
- Register maps
- errata workarounds
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds the Freescale ddr driver used on various PowerPC and
Layerscape SoCs. This is based on U-Boot-2019.01 but with many
adjustments:
- PowerPC support has been removed
- CPP #ifdeffery replaced with C
- No more global variables/functions expected from the driver,
configuration is passed by the board code which calls the driver
We already have the driver in the tree in an older version forked from
U-Boot-2013.04. This version lacks Layerscape support and many quirks
in the driver are PowerPC specific. Since the existing driver should
work on all known PowerPC and PowerPC is a dead end I decided not to
improve the existing driver and instead add a new Layerscape specific
driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds ethernet support for the Freecale Layerscape SoCs. The
architecture in these SoCs is called "Data Path Acceleration
Architecture" (DPAA). It is comprised of:
- The Queue Manager (QMan)
- Buffer Manager (BMan)
- Frame Manager (FMan)
- Multirate Ethernet Media Access Controller (mEMAC)
The code is based on the corresponding U-Boot driver enriched with
device tree parsing and proper device driver support.
Tested on LS1046a, should work on other SoCs aswell with some minor
quirks. SerDes support has been removed for now.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The Freescale QUICC Engine found on Layerscape SoCs needs firmware
loaded. This adds support for loading such a firmware.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Based on kernel 5.0-rc6 update at91 clk support
to match the new PMC bindings.
Manually added all changes done in the kernel from 4.9-rc3 to 5.0-rc6.
New drivers required was added as seperate commits.
This includes dt-compat code required to support at91sam5d3,
as this is not yet ported to use the new PMC bindings.
clk-programmable saw some extra changes - it had never been bulit.
It is used only by at91sama5d2 - and barebox has no board support for
this cpu (yet).
The CONFIG_SOC symbols is used to select the relevant drivers.
CONFIG_SOC_SAM9 selects several drivers, and in the future
this can be split to keep the image size down.
In the kernel CLK_OF_DECLARE_DRIVER() can be used for a two step init.
In barebox this is a simple one step init.
It was added to have less differences between the kernel and the barebox
versions of the drivers.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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