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Fixes: 4fafb35d925e5 ("kbuild: cherry-pick changes from Linux v5.0-rc3")
The change cherry-picked from the Kernel commit 7d0ea2524202 ("kbuild: use
'else ifeq' for checksrc to improve readability") also removed the
trailing semicolons from the cmd_*checksrc lines. These were removed in
kernel commit e5d289100d ("kbuild: remove trailing semicolon from cmd_*
passed to if_changed_rule"), but seems the barebox Kbuild version is not
yet ready for this change. Without the semicolons a make C=1 build fails
with:
No such file: echo
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
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Not synced completely.
Just cherry-picking low-hanging fruits.
0b35786d77ba kbuild: call make once for all targets when O=.. is used
5e54d5e5fbc1 kbuild: kill EXTRA_ARFLAGS
836caba77c29 kbuild: kill backward compatibility checks
3156fd0529b5 kbuild: fix some minor typoes
b8b0618cf6fa kbuild: remove extra ifdef/endif of top Makefile
16f890988114 kbuild: Remove reference to uninitialised variable
9319f4539c18 kbuild: support simultaneous "make %config" and "make all"
9d5db8949f1e scripts/Makefile.clean: clean also $(extra-m) and $(extra-)
a4954fd7724c kbuild: remove obj-n and lib-n handling
371fdc77af44 kbuild: collect shorthands into scripts/Kbuild.include
a29b82326ed4 kbuild: Remove duplicate $(cmd) definition in Makefile.clean
a1e7b7bb1ab5 Makefile: sort list of defconfig targets in make help output
34948e0bbf98 kbuild: Drop support for clean-rule
4218affdf57f kbuild: remove warning about "make depend"
9c8fa9bc08f6 kbuild: fix if_change and friends to consider argument order
39a33ff80a25 kbuild: remove cc-option-align
a7f924190924 kbuild: add %.dtb.S and %.dtb to 'targets' automatically
54a702f70589 kbuild: mark $(targets) as .SECONDARY and remove .PRECIOUS markers
9564a8cf422d Kbuild: fix # escaping in .cmd files for future Make
bd412d81b7ea kbuild: .PHONY is not a variable, but PHONY is
6916162c7308 kbuild: remove duplicated comments about PHONY
d6c6ab93e17f kbuild: remove deprecated host-progs variable
7d0ea2524202 kbuild: use 'else ifeq' for checksrc to improve readability
3f80babd9ca4 kbuild: remove unused cc-fullversion variable
bd352a739fde kbuild: remove unused baseprereq
b421b8a6cb87 kbuild: remove unused archmrproper
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Linux commit b23d1a241f4eb44ae55785c9b65274717c8e2c1e
(adjust commit log for barebox)
This will be needed for Barebox to switch to the compile-time
generation of lexers and parsers.
Files generated by if_changed* must be added to 'targets' to include
*.cmd files. Otherwise, they would be regenerated every time.
The build system automatically adds objects to 'targets' where
appropriate, such as obj-y, extra-y, etc. but does nothing for
intermediate files. So, each Makefile needs to add them by itself.
There are some common cases where objects are generated by chained
rules. Lexers and parsers are compiled like follows:
%.lex.o <- %.lex.c <- %.l
%.tab.o <- %.tab.c <- %.y
They are common patterns, so it is reasonable to take care of them
in the core Makefile instead of requiring each Makefile to do so.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Linux commit 591f66899784ae0afa13ff9a3eb5ce0a4358e48b
The variable "targets" contains object paths for which existing .*.cmd
files should be included.
scripts/Makefile.build automatically adds $(MAKECMDGOALS) to "targets"
as follows:
targets += $(extra-y) $(MAKECMDGOALS) $(always)
The $(MAKECMDGOALS) is a PHONY target in several places. PHONY targets
never create .*.cmd files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The comment in scripts/Makefile.build says as follows:
We would rather have a list of rules like
foo.o: $(foo-objs)
but that's not so easy, so we rather make all composite objects depend
on the set of all their parts
This commit makes it possible!
For example, assume a Makefile like this
obj-m = foo.o bar.o
foo-objs := foo1.o foo2.o
bar-objs := bar1.o bar2.o
Without this patch, foo.o depends on all of
foo1.o foo2.o bar1.o bar2.o.
It looks funny that foo.o is regenerated when bar1.c is updated.
Now we can handle the dependency of foo.o and bar.o separately.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Michal Marek <mmarek@suse.cz>
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We had pbl_cc__o_c instead of pbl_cc_o_c. This caused all pbl object
files to be rebuilt everytime due to missing .cmd file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Otherwise the pbl files do not get rebuilt when the CFLAGS change.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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This will allow to link compiled object to the built-in-pbl.o across the source
tree that will be finally link to the pbl.
Now we compile the source %.c in pbl-%.o and provide -D__PBL__
so we can known in the source when it's compile for barebox or the pbl.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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import from linux 3.5-rc5
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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When building sandbox with ccache, one would hit warnings such as:
warning: 'struct mmsghdr' declared inside parameter list
on random files; a way to reproduce this issue is to build a simple
file doing just:
#include <sys/socket.h>
int main(void) {
return 0;
}
gcc -Wall -P -c -o foo foo.c
But actually the -P flag is only useful when generating non-C files,
such as linker scripts in the case of barebox. Removing the -P flag
from all the gcc invocations, except when generating .lds files makes
the warning go away. It turns out that this is what
linux/scripts/Makefile.build also does nowadays.
Signed-off-by: Loïc Minier <loic.minier@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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add missing Kconfig
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