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Booting Layerscape from QSPI is a bit tricky and the approach we take is
different from the one U-Boot has taken, so it's worth writing and
reading the following explanation.
The QSPI controller can map the Flash contents into the memory space (On
LS1046a at 0x40000000). The PBL unit uses this to read the RCW from this
memory window. The Layerscape SoCs have a PowerPC history, so it seemed
appropriate for the designers to let the QSPI controller operate in
big endian mode by default. To let the SoC see the correct RCW we have
to write the RCW and PBI data with be64 endianess. Our PBL image tool
pokes the initial binary into the SoC internal SRAM using PBI data as
done with SD/MMC boot aswell. barebox then changes the QSPI controller
endianess to le64 to properly read the barebox binary (placed at an
flash offset of 128KiB, so found in memory at 0x40020000) into SDRAM and
jumps to it.
U-Boot has another approach. Here the initial binary is executed in
place directly at 0x40100000. This means the QSPI controller endianess
must be swapped inside the PBI data. This has the effect that the whole
RCW/PBI data must be 64bit endianess swapped *except* the very last word
of the PBI data which contains the CRC command and is read already with
changed endianess. As a conclusion when porting QSPI PBI files from U-Boot
to barebox skip commands changing the endianess in the QSPI controller
and make sure the image is executed in internal SRAM and not in the
Flash memory window.
Lines like this should be removed:
09550000 000f400c
This sets the binary execution address:
09570604 40100000
For barebox it should be changed to 0x10000000.
As a result the PBI files can probably be unified between SD and QSPI
boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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The PBL image tool includes two commands into the image. These are executed
after the initial image has been uploaded but before the final CRC
check. These commands are "flush" and "wait". According to the reference
manual a "flush" command can be used to read back the the value just
written to CCSR register space in order to let the previous write
complete. This seems unnecessary as the last write was never to the CCSR
register space. The "wait" command also seems unnecessary as the time
parameter is 0. As all this end_cmd stuff goes back to the PowerPC times
and everything still seems to work on Arm let's just remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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This adds the Layerscape image tool based on the corresponding U-Boot
tool. PBL in the name is for "Pre-Boot Loader", just like the barebox
PBL support, but here the name is for the Layerscape image format which
has the same name.
Layerscape SoCs load the initial image portion into SRAM, so only a
fraction of the barebox image can initially be loaded. This tool expects
the full barebox image and the size of the PBL part of this image
specified to the -m option. The full barebox image is then placed in the
output image at offset 128KiB.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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