From 268a356206c8c42f7346a822d6565377bd33304c Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 16 Dec 2018 21:18:54 -0800 Subject: PCI: dwc: all: Rename cfg_read/cfg_write to read/write No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do anything specific to access configuration space. It can be just renamed to dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Bjorn Helgaas Reviewed-By: Joao Pinto CC: Jingoo Han CC: Murali Karicheri CC: Stanimir Varbanov CC: Pratyush Anand Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- drivers/pci/pcie-designware.c | 12 ++++++------ drivers/pci/pcie-designware.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index 2ddda31925..74769de7fa 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -32,7 +32,7 @@ static unsigned long global_io_offset; -int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) +int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { *val = 0; @@ -53,7 +53,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) return PCIBIOS_SUCCESSFUL; } -int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) +int dw_pcie_write(void __iomem *addr, int size, u32 val) { if ((uintptr_t)addr & (size - 1)) return PCIBIOS_BAD_REGISTER_NUMBER; @@ -109,7 +109,7 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, if (pp->ops->rd_own_conf) return pp->ops->rd_own_conf(pp, where, size, val); - return dw_pcie_cfg_read(pp->dbi_base + where, size, val); + return dw_pcie_read(pp->dbi_base + where, size, val); } static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, @@ -118,7 +118,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, if (pp->ops->wr_own_conf) return pp->ops->wr_own_conf(pp, where, size, val); - return dw_pcie_cfg_write(pp->dbi_base + where, size, val); + return dw_pcie_write(pp->dbi_base + where, size, val); } static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, @@ -376,7 +376,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, type, cpu_addr, busdev, cfg_size); - ret = dw_pcie_cfg_read(va_cfg_base + where, size, val); + ret = dw_pcie_read(va_cfg_base + where, size, val); if (pp->num_viewport <= 2) dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_IO, pp->io_mod_base, @@ -415,7 +415,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, type, cpu_addr, busdev, cfg_size); - ret = dw_pcie_cfg_write(va_cfg_base + where, size, val); + ret = dw_pcie_write(va_cfg_base + where, size, val); if (pp->num_viewport <= 2) dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_IO, pp->io_mod_base, diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h index 3171adfe78..fb9d2fdb64 100644 --- a/drivers/pci/pcie-designware.h +++ b/drivers/pci/pcie-designware.h @@ -140,8 +140,8 @@ struct pcie_host_ops { u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg); void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val); -int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val); -int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val); +int dw_pcie_read(void __iomem *addr, int size, u32 *val); +int dw_pcie_write(void __iomem *addr, int size, u32 val); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); -- cgit v1.2.3