From 285a05487a6bb9ef023163a62006524a17835e0a Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 19 Jun 2017 07:40:39 -0700 Subject: i.MX: clk: Remove imx_clk_pllv3_locked() Remove imx_clk_pllv3_locked() which was introduced for the sake of Vybrid platform. The same effect (waiting on 'locked' bit) can be achived with vanilla clk_pllv3_enable/disable, which make said function unnecessary. Signed-off-by: Andrey Smirnov Signed-off-by: Sascha Hauer --- drivers/clk/imx/clk-pllv3.c | 24 ------------------------ drivers/clk/imx/clk-vf610.c | 16 ++++++++++++++-- drivers/clk/imx/clk.h | 4 ---- 3 files changed, 14 insertions(+), 30 deletions(-) diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index a14d36e565..0e55a63e92 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -41,8 +41,6 @@ struct clk_pllv3 { u32 div_mask; u32 div_shift; const char *parent; - void __iomem *lock_reg; - u32 lock_mask; u32 ref_clock; u32 power_bit; }; @@ -354,9 +352,6 @@ static int clk_pllv3_sys_vf610_set_rate(struct clk *clk, unsigned long rate, writel(mfn, pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET); writel(mfd, pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET); - while (!(readl(pll->lock_reg) & pll->lock_mask)) - ; - return 0; } @@ -427,22 +422,3 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, return &pll->clk; } - -struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name, - const char *parent, void __iomem *base, - u32 div_mask, void __iomem *lock_reg, u32 lock_mask) -{ - struct clk *clk; - struct clk_pllv3 *pll; - - clk = imx_clk_pllv3(type, name, parent, base, div_mask); - if (IS_ERR(clk)) - return clk; - - pll = to_clk_pllv3(clk); - - pll->lock_reg = lock_reg; - pll->lock_mask = lock_mask; - - return clk; -} diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c index 5469840bfc..49d66fb592 100644 --- a/drivers/clk/imx/clk-vf610.c +++ b/drivers/clk/imx/clk-vf610.c @@ -192,8 +192,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); - clk[VF610_CLK_PLL1] = imx_clk_pllv3_locked(IMX_PLLV3_SYS_VF610, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1, PLL_LOCK, BIT(6)); - clk[VF610_CLK_PLL2] = imx_clk_pllv3_locked(IMX_PLLV3_SYS_VF610, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1, PLL_LOCK, BIT(5)); + clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); + clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_SYS_VF610, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2); clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); @@ -478,6 +478,18 @@ static int vf610_switch_cpu_clock_to_500mhz(void) return -EINVAL; } + /* + * Code below alters the frequency of PLL1, and doing so would + * require us to wait for PLL1 lock before proceeding to + * select it as a clock source again. + * + * We achive this by relying on PLL1 being disabled implicitly + * by selecting different source for "sys_sel", and then + * consecutively enabled (which would result in busy waiting + * on 'lock' bit) as a part of setting "pll1_pfd_sel" as a + * source for "sys_sel". + * + */ ret = clk_set_parent(clk[VF610_CLK_SYS_SEL], clk[VF610_CLK_PLL2_BUS]); if (ret < 0) { pr_crit("Unable to re-parent '%s'\n", diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 8da806403f..c46c2614d9 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -126,10 +126,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent, void __iomem *base, u32 div_mask); -struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name, - const char *parent, void __iomem *base, - u32 div_mask, void __iomem *lock_reg, u32 lock_mask); - struct clk *imx_clk_pfd(const char *name, const char *parent, void __iomem *reg, u8 idx); -- cgit v1.2.3